# US 2008/0185668 A1 · Memory device and method of fabricating the same

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- Number: US 2008/0185668 A1
- Document ID: US20080185668A1
- Status: Published application
- Kind: A1
- Application number: 12/007,819
- Filed: 2008-01-16
- Published: 2008-08-07
- Earliest claimed: 2007-01-16
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Min-Sang Kim; Sung-Young Lee; Sung-Min Kim; Eun-Jung Yun; Dong-Won Kim; Dong-Gun Park
- Web page: https://patentgrep.com/patent/US20080185668A1

## CPC

- G11C 11/56: using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- G11C 13/025: {using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes}
- G11C 23/00: Digital stores characterised by movement of mechanical parts to effect storage, e.g. using balls; Storage elements therefor
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 62/121: {oriented parallel to substrates}
- G11C 2213/16: Memory cell being a nanotube, e.g. suspended nanotube
- G11C: STATIC STORES (semiconductor memory devices H10B)
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A memory device may include a substrate, a bit line, at least a first lower word line, at least a first trap site, a pad electrode, at least a first cantilever electrode, and/or at least a first upper word line. The bit line may be formed on the substrate in a first direction. The first lower word line and the first trap site may be insulated from the bit line and formed in a second direction crossing the bit line. The pad electrode may be insulated at sidewalls of the first lower word line and the first trap site and connected to the bit line. The first cantilever electrode may be formed in the first direction, connected to the pad electrode, floated on the first trap site with at least a first lower vacant space, and/or configured to be bent in a third direction. The first upper word line may be formed on the first cantilever electrode in the second direction with at least a first upper vacant space.

## Claims

### Claim 1

A memory device, comprising:
a substrate;
a bit line on the substrate in a first direction;
at least a first lower word line and at least a first trap site insulated from the bit line and in a second direction crossing the bit line;
a pad electrode insulated at sidewalls of the first lower word line and the first trap site and connected to the bit line;
at least a first cantilever electrode in the first direction, connected to the pad electrode, floated on the first trap site with at least a first lower vacant space, and configured to be bent in a third direction; and
at least a first upper word line on the first cantilever electrode in the second direction with at least a first upper vacant space.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the pad electrode is electrically insulated from the first lower word line and the first trap site by a second interlayer insulating layer at the sidewalls of the first lower word line and the first trap site, the pad electrode in a contact hole in the second interlayer insulating layer which selectively exposes the bit line.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein the first trap site includes a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer stacked on the first lower word line.

### Claim 4 (depends on 1)

The memory device of claim 1, further comprising:
a second lower word line and a second trap site insulated from the bit line and in the second direction crossing the bit line, the first lower word line and first trap site separated from the second lower word line and second trap site by a trench in the second direction, each of the first lower word line and first trap site and the second lower word line and second trap site being insulated from the bit line by a first interlayer insulating layer, wherein
the pad electrode is insulated from the first and second lower word lines and the first and second trap sites by a second interlayer insulating layer to fill sidewalls of the first and second lower word lines opposite to the trench and sidewalls of the first and second trap sites opposite to the trench, and
the pad electrode is in a contact hole in the second interlayer insulating layer at both sides of the first and second lower word lines and the first and second trap sites opposite to each other, the contact hole exposing the bit line through the second interlayer insulating layer;
a second cantilever electrode in the first direction and configured to be bent in the third direction, the first and second cantilever electrodes supported on the pad electrode by the second interlayer insulating layer, the second cantilever electrode floated with a second lower vacant space on the second trap site, the first and second cantilever electrodes divided by the trench;
a third interlayer insulating layer on the first and second cantilever electrodes corresponding to the pad electrode; and
a second upper word line on the second cantilever electrode in the second direction with a second upper vacant space, the first and second upper word lines supported by the third interlayer insulating layer.

### Claim 5 (depends on 4)

The memory device of claim 4, wherein the pad electrode is electrically connected to the first and second cantilever electrodes.

### Claim 6 (depends on 4)

The memory device of claim 4, wherein the first and second trap sites are configured to tunnel and capture the charges applied to the first and second lower word lines, respectively, and maintain the first and second cantilever electrodes in the bent position contacting the first and second trap sites if the charges applied to the first and second lower word lines are removed.

### Claim 7 (depends on 4)

The memory device of claim 4, wherein the first and second cantilever electrodes include at least one of titanium, nitride titanium, and carbon nanotubes.

### Claim 8 (depends on 4)

The memory device of claim 4, further comprising:
first and second spacers in the second direction at both sides of the first and second lower word lines opposite to each other centering the trench and at both sides of the first and second trap sites opposite to each other centering the trench.

### Claim 9 (depends on 8)

The memory device of claim 8, wherein the first and second spacers are exposed by the contact hole on the top of the bit line, and the remainder of the spacers are filled at both sides by the second interlayer insulating layer.

### Claim 10 (depends on 4)

The memory device of claim 4, wherein the trench is in the second direction crossing the bit line and exposes the top of the first interlayer insulating layer.

### Claim 11 (depends on 10)

The memory device of claim 10, further comprising:
a fourth interlayer insulating layer on a top portion of the trench and configured to seal the inside of the trench.

### Claim 12

A method of fabricating a memory device, the method comprising:
forming a bit line on a substrate in a first direction;
forming a stack including a first interlayer insulating layer, a lower word line, a trap site and a first sacrificial layer in a second direction crossing the bit line;
forming a second interlayer insulating layer to fill sidewalls of the stack and including a contact hole to expose the bit line at the sidewalls of the stack;
forming a pad electrode inside the contact hole;
forming a cantilever electrode on the pad electrode and the second interlayer insulating layer in the first direction, to be connected to the top of the first sacrificial layer;
forming a second sacrificial layer and an upper word line on the cantilever electrode and the second interlayer insulating layer formed on the stack in the second direction;
forming a third interlayer insulating layer around sidewalls of the second sacrificial layer and the upper word line;
forming a trench to expose the first interlayer insulating layer at the bottom, by removing the upper word line, the second sacrificial layer, the cantilever electrode, the first sacrificial layer, the trap site and the lower word line in the second direction; and
forming a space above and under the cantilever electrode, by removing the first sacrificial layer and the second sacrificial layer exposed by the trench.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
forming a spacer at the sidewalls of the stack before forming the second interlayer insulating layer.

### Claim 14 (depends on 12)

The method of claim 12, wherein the contact hole is formed in the second interlayer insulating layer for selectively exposing the bit line at both sides of the stack by forming a silicon oxide layer to fill the sidewalls the stack and removing at least a portion of the silicon oxide layer to expose the first sacrificial layer.

### Claim 15 (depends on 12)

The method of claim 12, wherein the pad electrode is formed by filling the contact hole with at least one of conductive metal and polysilicon, and removing the at least one of conductive metal and polysilicon to expose the first sacrificial layer and the second interlayer insulating layer.

### Claim 16 (depends on 12)

The method of claim 12, wherein the cantilever electrode is formed on the bit line with a critical dimension substantially the same as a critical dimension of the bit line.

### Claim 17 (depends on 12)

The method of claim 12, wherein if the first and second sacrificial layers are formed of polysilicon materials, the polysilicon materials are isotropically etched to be removed by at least one of a wet etching method and a dry etching method.

### Claim 18 (depends on 17)

The method of claim 17, wherein
an isotropic etching solution used for the wet etching method includes a mixed solution including a nitric acid, a fluoric acid, and an acetic acid mixed with deionized water at a concentration, and
an isotropic reaction gas used for the dry etching method includes a carbon fluoride series gas.

### Claim 19 (depends on 12)

The method of claim 12, further comprising:
removing a portion of the upper word line, a portion of the second sacrificial layer, a portion of the cantilever electrode, and a portion of the first sacrificial layer to form a dummy trench exposing the trap site and sidewalls of the first sacrificial layer and the second sacrificial layer;
removing at least a portion of the first sacrificial layer and at least a portion of the second sacrificial layer to form the space above and below the cantilever electrode; and
removing a portion of the trap site and a portion of the lower word line exposed at the bottom of the dummy trench to form the trench exposing the first interlayer insulating layer.

### Claim 20 (depends on 12)

The method of claim 12, further comprising:
forming a fourth interlayer insulating layer on a top portion of the trench to seal the inside of the trench.