# US 2008/0185667 A1 · Thin Film Semiconductor Device and Method for Manufacturing the Same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2008/0185667 A1 - Document ID: US20080185667A1 - Status: Published application - Kind: A1 - Application number: 11/663,057 - Filed: 2004-09-17 - Published: 2008-08-07 - Earliest claimed: 2004-09-17 - Inventors: Kenichi Yoshino; Akito Hara; Michiko Takei; Takuya Hirano - Web page: https://patentgrep.com/patent/US20080185667A1 ## CPC - H10D 86/021: {of multiple TFTs} - H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes} - H10D 30/6731: {Top-gate only TFTs} - H10D 30/6739: {Conductor-insulator-semiconductor electrodes} - H10D 30/6745: {Polycrystalline or microcrystalline silicon} - H10D 30/794: {comprising conductive materials, e.g. silicided source, drain or gate electrodes} - H10D 64/01316: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al} - H10D 84/0179: {the gate conductors having different shapes or dimensions} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 86/01: Manufacture or treatment - H10D 86/40: characterised by multiple TFTs - H10D 86/60: wherein the TFTs are in active matrices - H10P 30/204: {into Group IV semiconductors} - H10P 30/21: {of electrically active species} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract An Mo film (6) is formed on a SiO2 film (5) by particularly using the film thickness and the deposition temperature (ambient temperature in a sputtering chamber) as the primary parameters and adjusting the film thickness to be within the range from 100 nm to 500 nm (more preferably 100 nm to 300 nm) and the deposition temperature to be within the range from 25° C. to 300° C., so as to control residual stress to have a predetermined value of 300 MPa or greater and to be oriented to increase the in-plane lattice constant. There can be thus provided a reliable CMOSTFT in which desired strain is easily and reliably imparted to polysilicon thin films (4a and 4b) to improve the mobility therein without adding an extra step of imparting the strain to the silicon thin film. ## Claims ### Claim 1 A thin film semiconductor device comprising: an insulating substrate; a semiconductor thin film patterned on the insulating substrate; and a gate electrode patterned on the semiconductor thin film via a gate insulating film, wherein the gate electrode has a film thickness ranging from 100 nm to 500 nm and has residual stress of 300 MPa or greater oriented to increase the in-plane lattice constant. ### Claim 2 (depends on 1) The thin film semiconductor device according to claim 1, wherein the film thickness of the gate electrode ranges from 100 nm to 300 nm. ### Claim 3 (depends on 2) The thin film semiconductor device according to claim 2, wherein the semiconductor thin film is a silicon film whose crystal grain size is 400 nm or greater at least in the channel region of the silicon film. ### Claim 4 (depends on 2) The thin film semiconductor device according to claim 2, wherein the semiconductor thin film is a silicon film and the wave number of the Raman peak in Raman scattering is 517/cm or smaller at least in the channel region of the silicon film. ### Claim 5 (depends on 2) The thin film semiconductor device according to claim 2, wherein the semiconductor thin film is a silicon film and the wave number of the Raman peak in Raman scattering at least in the channel region of the silicon film shifts to the low frequency side by at least 0.2/cm relative to the wave number obtained before the formation of the gate electrode. ### Claim 6 (depends on 2) The thin film semiconductor device according to claim 2, wherein the gate electrode includes one metal selected from a group of metals, Mo, W, Ti, Nb, Re and Ru, an alloy of a plurality of metals selected from the group of metals or a laminated structure of a plurality of metals selected from the group of metals. ### Claim 7 (depends on 2) The thin film semiconductor device according to claim 2, wherein the semiconductor thin film comprises a pair of the semiconductor thin films, each of which provided with the gate electrode thereon via the gate insulating film, and one of the gate electrodes is formed to be thinner than the other one of the gate electrodes. ### Claim 8 (depends on 7) The thin film semiconductor device according to claim 7, wherein the number of layers of the other one of the gate electrodes is greater than that of the one of the gate electrodes. ### Claim 9 A method for manufacturing a thin film semiconductor device comprising the steps of: pattering a semiconductor thin film on an insulating substrate; and patterning a gate electrode on the semiconductor thin film via a gate insulating film, wherein the gate electrode is formed such that the film thickness thereof is adjusted to be a value ranging from 100 nm to 500 nm so as to create residual stress of 300 MPa or greater oriented to increase the in-plane lattice constant, and the residual stress induces tensile stress in the semiconductor thin film, so that the in-plane lattice constant thereof is controlled to be larger than that will be achieved when the tensile stress is not applied. ### Claim 10 (depends on 9) The method for manufacturing a thin film semiconductor device according to claim 9, wherein the gate electrode is formed such that the film thickness thereof is adjusted to be a value ranging from 100 nm to 300 nm so as to create residual stress of 300 MPa or greater oriented to increase the in-plane lattice constant. ### Claim 11 (depends on 9) The method for manufacturing a thin film semiconductor device according to claim 9, wherein the gate electrode is formed such that the film thickness thereof is adjusted to be a value ranging from 100 nm to 300 nm and the ambient temperature during deposition is adjusted to be a value ranging from 25° C. to 300° C. so as to create residual stress of 300 MPa or greater oriented to increase the in-plane lattice constant. ### Claim 12 (depends on 11) The method for manufacturing a thin film semiconductor device according to claim 11, wherein after the semiconductor thin film in an amorphous state is formed on the insulating substrate, laser light is applied to the semiconductor thin film to crystallize the semiconductor thin film. ### Claim 13 (depends on 11) The method for manufacturing a thin film semiconductor device according to claim 11, wherein the semiconductor thin film is a silicon film and the crystal grain size at least in the channel region of the silicon film is 400 nm or greater. ### Claim 14 (depends on 11) The method for manufacturing a thin film semiconductor device according to claim 11, wherein the gate electrode is made of material including one metal selected from a group of metals, Mo, W, Ti, Nb, Re and Ru, an alloy of a plurality of metals selected from the group of metals or a laminated structure of a plurality of metals selected from the group of metals. ### Claim 15 (depends on 11) The method for manufacturing a thin film semiconductor device according to claim 11 wherein a pair of the semiconductor thin films are simultaneously formed on the insulating substrate, and the gate electrode is formed on each of the semiconductor thin films via the gate insulating film such that one of the gate electrodes is thinner than the other one of the gate electrodes. ### Claim 16 (depends on 15) The method for manufacturing a thin film semiconductor device according to claim 15, wherein after the gate electrodes are simultaneously formed to the film thickness of the other one of the gate electrodes, only the one of the gate electrodes is etched to be thinner. ### Claim 17 (depends on 15) The method for manufacturing a thin film semiconductor device according to claim 15, wherein after the gate electrodes are simultaneously formed to the film thickness of the other one of the gate electrodes and an impurity is introduced into the semiconductor thin film on which the one of the gate electrodes is formed, only the one of the gate electrodes is etched to be thinner. ### Claim 18 (depends on 15) The method for manufacturing a thin film semiconductor device according to claim 15, wherein after a plurality of metal layers are laminated to simultaneously form the gate electrodes to the film thickness of the other one of the gate electrodes, at least the top metal layer is etched only for the one of the gate electrodes to reduce the thickness thereof. ### Claim 19 (depends on 15) The method for manufacturing a thin film semiconductor device according to claim 15, wherein after a plurality of metal layers are laminated to simultaneously form the gate electrodes to the film thickness of the other one of the gate electrodes and an impurity is introduced into the semiconductor thin film on which the one of the gate electrodes is formed, at least the top metal layer is etched only for the one of the gate electrodes to reduce the thickness thereof.