# US 2008/0185666 A1 · Field effect transistors including variable width channels and methods of forming the same

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- Number: US 2008/0185666 A1
- Document ID: US20080185666A1
- Status: Published application
- Kind: A1
- Application number: 12/024,319
- Filed: 2008-02-01
- Published: 2008-08-07
- Earliest claimed: 2007-02-05
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Seung-Han Yoo; Dae-Lim Kang; Young-Chan Lee
- Web page: https://patentgrep.com/patent/US20080185666A1

## CPC

- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/608: {having non-planar bodies, e.g. having recessed gate electrodes}
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A field effect transistor includes a first substrate region having a channel region and a second substrate region where a heavily doped region is formed. The channel region includes a first portion having a first width and a second portion having a second width larger than the first width. Related fabrication methods are also described.

## Claims

### Claim 1

A field effect transistor comprising:
a substrate;
a field insulation layer disposed in the substrate, the field insulation layer defining a first substrate region and a second substrate region spaced apart from each other;
a gate on the first substrate region;
a channel region defined in the first substrate region under the gate, the channel region comprising a first portion having a first width and a second portion having a second width, along a channel width direction that is transverse to a direction from the first substrate region to the second substrate region;
a heavily doped region in the second substrate region; and
a lightly doped region in the substrate surrounding a sidewall and a bottom surface of the heavily doped region,
wherein the first portion is interposed between the second substrate region and the second portion, the first portion is adjacent to the field insulation layer between the first and the second substrate regions, and the first width is smaller than the second width.

### Claim 2 (depends on 1)

The field effect transistor of claim 1, wherein the second substrate region has a third width along the channel width direction, and the second width is larger than the third width.

### Claim 3 (depends on 2)

The field effect transistor of claim 2, wherein the lightly doped region has a fourth width along the channel width direction, and the second width is larger than the fourth width.

### Claim 4 (depends on 2)

The field effect transistor of claim 2, wherein the first width is equal to or smaller than the third width and is equal to or larger than half of the third width.

### Claim 5 (depends on 1)

The field effect transistor of claim 1, wherein the gate extends along a portion of the field insulation layer interposed between the first and the second substrate regions.

### Claim 6 (depends on 1)

The field effect transistor of claim 1 further comprising a heavily doped source region in the first substrate region at one side of the gate.

### Claim 7 (depends on 6)

The field effect transistor of claim 6, wherein a width along the channel width direction of the first substrate region where the source heavily doped region is formed is equal to the second width.

### Claim 8 (depends on 1)

The field effect transistor of claim 1, wherein the field insulation layer defines the first substrate region and a pair of the second substrate regions, the first substrate region is interposed between the pair of the second substrate regions; the gate is on an entire surface of the first substrate region; the channel region comprises a pair of the first portions and the second portion, the second portion is interposed between the pair of the first portions; and the channel region has a symmetrical structure centered about the second portion.

### Claim 9 (depends on 8)

The field effect transistor of claim 8, wherein a pair of the heavily doped regions are in the pair of the second substrate regions, respectively; a pair of the lightly doped regions are disposed on opposite sides of the channel region, respectively; and the pair of the lightly doped regions surround the pair of the heavily doped regions, respectively.

### Claim 10 (depends on 1)

The field effect transistor of claim 1, wherein a width of the channel region gradually increases from the first portion to the second portion.

### Claim 11 (depends on 1)

The field effect transistor of claim 1, wherein a width of the channel region increases in at least one step from the first portion to the second portion.

### Claim 12 (depends on 1)

The field effect transistor of claim 1, wherein a side connecting edges of the first and the second portions in the channel region is a concave-curved side or a convex-curved side.

### Claim 13

A method of forming a field effect transistor comprising:
forming a field insulation layer defining a first substrate region and a second substrate region spaced apart from each other in a substrate;
forming a lightly doped region in the substrate;
forming a gate on the first substrate region; and
forming a heavily doped region in the second substrate region,
wherein a channel region defined in the first substrate region under the gate comprises a first portion having a first width and a second portion having a second width in a channel width direction that is transverse to a direction from the first substrate region to the second substrate region, the first portion is interposed between the second substrate region and the second portion and is adjacent to the field insulation layer between the first and the second substrate regions, the first width is smaller than the second width, and the lightly doped region surrounds a sidewall and a bottom surface of the heavily doped region.

### Claim 14 (depends on 13)

The method of claim 13, wherein forming the lightly doped region and the field insulation layer comprise:
forming a first hard mask pattern and a second hard mask pattern spaced from each other on the substrate;
forming a mask pattern having an opening on the substrate;
implanting dopant ions in a low dose to a portion of the substrate using as a mask the first and the second hard mask patterns and the mask pattern;
removing the mask pattern;
forming the field insulation layer on the substrate where the first and the second hard mask patterns are not formed; and
removing the first and the second hard mask patterns,
wherein the opening defines the lightly doped region.

### Claim 15 (depends on 14)

The method of claim 14, wherein the implanted low-dose dopant ions are diffused to the second substrate region by a thermal process to form the lightly doped region.

### Claim 16 (depends on 14)

The method of claim 14, wherein forming the lightly doped region further comprises implanting the second low-dose dopant ions through the second substrate region.

### Claim 17 (depends on 13)

The method of claim 13, wherein the second width is formed larger than a width of the lightly doped region in the channel width direction.

### Claim 18 (depends on 13)

The method of claim 13, wherein the second substrate region has a third width along the channel width direction, and the first width is equal to or smaller than the third width and is equal to or larger than half of the third width.

### Claim 19 (depends on 13)

The method of claim 13 further comprising forming a heavily doped source region in the first substrate region on one side of the gate.

### Claim 20 (depends on 13)

The method of claim 13, wherein the field insulating layer defines the first substrate region and a pair of the second substrate regions, the first substrate region interposed between the pair of the second substrate regions,
the gate is formed on an entire surface of the first substrate region,
the channel region comprises the pair of the first portions and the second portion, the second portion is interposed between the pair of the first portions,
the channel region is formed in a symmetrical structure centered about the second portion,
a pair of the heavily doped region are formed in the pair of the second substrate regions, respectively, and
a pair of the lightly doped region are formed on opposite sides of the channel region to surround the pair of the heavily doped regions, respectively.

### Claim 21 (depends on 13)

The method of claim 13, wherein a width of the channel region is gradually increased from the first portion to the second portion.

### Claim 22 (depends on 13)

The method of claim 13, wherein a width of the channel region increases in at least one step from the first portion to the second portion.

### Claim 23 (depends on 13)

The method of claim 13, wherein a side connecting edges of the first and the second portions of the channel region is a concave-curved side or a convex-curved side.

### Claim 24

A field effect transistor comprising:
a substrate;
a field insulation layer in the substrate that is configured to define first and second substrate regions that are spaced apart from one another, the field insulation layer that defines the first substrate region having different widths at corresponding different lengths away from the second substrate region so that the first substrate region also has different widths at corresponding different lengths away from the second substrate region;
a gate on at least a portion of the first substrate region that has different widths at corresponding different lengths away from the second substrate region; and
a source/drain region in the second substrate region.

### Claim 25 (depends on 24)

The field effect transistor of claim 24 wherein the field insulation layer that defines the first substrate region increases in width as a function of increasing length away from the second substrate region so that the first substrate region also increases in width as a function of increasing length away from the second substrate region.

### Claim 26 (depends on 24)

The field effect transistor of claim 24 wherein the field insulation layer that defines the first substrate region increases in width linearly, stepwise, concavely and/or convexly as a function of increasing length away from the second substrate region so that the first substrate region also increases in width linearly, stepwise, concavely and/or convexly as a function of increasing length away from the second substrate region.

### Claim 27 (depends on 24)

The field effect transistor of claim 24 wherein the source/drain region comprises a heavily doped source/drain region in the second substrate region and a lightly doped source drain region in the second substrate region beneath the heavily doped source/drain region and extending to beneath the field insulation layer that defines the second substrate region.

### Claim 28 (depends on 24)

The field effect transistor of claim 24 wherein the source/drain region is a first source/drain region, the field effect transistor further comprising a second source/drain region in the first substrate region remote from the first source/drain region.

### Claim 29 (depends on 28)

The field effect transistor of claim 28 wherein the second source/drain region comprises a heavily doped source/drain region in the first substrate region and extending from the gate to the field insulation layer that defines the first substrate region and a lightly doped source drain region in the first substrate region beneath the heavily doped source/drain region and extending from the gate to beneath the field insulation layer that defines the first substrate region.

### Claim 30 (depends on 24)

The field effect transistor of claim 24 wherein the first substrate region includes a minimum width and wherein the second substrate region is of uniform width corresponding to the minimum width.

### Claim 31 (depends on 24)

The field effect transistor of claim 24 wherein the field insulation layer is configured to define a pair of second substrate regions, a respective one of which is on a respective opposite side of the first substrate region, the field insulation layer that defines the first substrate region having different widths at corresponding different lengths away from the second substrate regions so that the first substrate region also has different widths at corresponding different lengths away from the second substrate regions; the field effect transistor further comprising a source/drain region in each of the second substrate regions.

### Claim 32 (depends on 30)

The field effect transistor of claim 30 wherein the different widths are symmetrical about an axis of symmetry.