# US 2008/0185662 A1 · Structure and method for forming asymmetrical overlap capacitance in field effect transistors

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- Number: US 2008/0185662 A1
- Document ID: US20080185662A1
- Status: Published application
- Kind: A1
- Application number: 12/062,068
- Filed: 2008-04-03
- Published: 2008-08-07
- Earliest claimed: 2005-10-07
- Assignees: International Business Machines Corporation
- Inventors: Haining Yang
- Web page: https://patentgrep.com/patent/US20080185662A1

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10P 30/221: {characterised by the angle between the ion beam and the mask}
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for forming asymmetric spacer structures for a semiconductor device includes forming a spacer layer over at least a pair of adjacently spaced gate structures disposed over a semiconductor substrate. The gate structures are spaced such that the spacer layer is formed at a first thickness in a region between the gate structures and at a second thickness elsewhere, the second thickness being greater than said first thickness. The spacer layer is etched so as to form asymmetric spacer structures for the pair of adjacently spaced gate structures.

## Claims

### Claim 1

A semiconductor device, comprising:
at least a pair of field effect transistor (FET) structures including a pair of adjacently spaced gate structures formed over a semiconductor substrate;
each of said pair of FET structures having a pair of asymmetric spacer structures adjacent sidewalls thereof;
wherein inner spacer structures located in a region between said pair of gate structures are thinner than outer spacer structures located on the outside of said pair of gate structures.

### Claim 2 (depends on 1)

The device of claim 1, wherein said asymmetric spacer structures further comprise offset spacers used in the definition of halo and extension implantation regions.

### Claim 3 (depends on 1)

The device of claim 1, further comprising extensions implanted within said substrate, wherein said extensions corresponding to thinner offset spacers have a longer gate overlap than said extensions corresponding to thicker offset spacers.

### Claim 4 (depends on 1)

The device of claim 1, wherein said asymmetric spacer structures further comprise second spacers formed over offset spacers, used in the definition of source and drain regions.

### Claim 5 (depends on 4)

The device of claim 4, further comprising source and drain regions implanted within said substrate, wherein said source regions correspond to thinner second spacers and said drain regions correspond to thicker second spacers.

### Claim 6 (depends on 5)

The device of claim 5, wherein said source regions have shorter extensions than said drain regions.

### Claim 7 (depends on 1)

The device of claim 1, wherein a distance between said pair of adjacently spaced gate structures is about 1 to 3 times a height of said gate structures.

### Claim 8

A field effect transistor (FET) device, comprising:
a gate structure formed over a semiconductor substrate;
a first pair of spacer structures formed on sidewalls of said gate structure;
a second pair of spacer structures formed adjacent said first pair of spacer structures, said second pair of spacer structures having an asymmetrical thickness with respect to one another;
a source region and extension thereof implanted on one side of said gate structure; and
a drain region and extension thereof implanted on the other side of said gate structure;
wherein the extension of said source region has a different length than the extension of said drain region, in accordance with said asymmetrical thickness of said second pair of spacer structures.

### Claim 9 (depends on 8)

The FET device of claim 8, wherein said source region corresponds to a thinner one of said second pair of spacer structures and said drain regions corresponds to a thicker one of said second pair of spacer structures.

### Claim 10 (depends on 9)

The FET device of claim 9, wherein the extension of said source region is shorter than the extension of said drain region.

### Claim 11 (depends on 8)

The FET device of claim 8, wherein said first pair of spacer structures also have an asymmetrical thickness with respect to one another.

### Claim 12 (depends on 11)

The FET device of claim 11, wherein one of said source and drain extensions corresponding to a thinner one of said first pair of spacer structures has a longer gate overlap than the other of said source and drain extensions corresponding to a thicker one of said first pair of spacer structures.

### Claim 13 (depends on 12)

The FET device of claim 12, wherein the extension of said source region has a longer gate overlap than the extension of said drain region.