# US 2008/0185650 A1 · FinFET for device characterization

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- Number: US 2008/0185650 A1
- Document ID: US20080185650A1
- Status: Published application
- Kind: A1
- Application number: 11/701,348
- Filed: 2007-02-01
- Published: 2008-08-07
- Earliest claimed: 2007-02-01
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Hao-Yu Chen; Chang-Yun Chang; Cheng-Chuan Huang; Fu-Liang Yang
- Web page: https://patentgrep.com/patent/US20080185650A1

## CPC

- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/022: {having lightly-doped source or drain extensions selectively formed at the sides of the gates}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method and system is disclosed for providing access to the body of a FinFET device. In one embodiment, a FinFET device for characterization comprises an active fin comprising a source fin, a depletion fin, and a drain fin; a side fin extending from the depletion fin and coupled to a body contact for providing access for device characterization; and a gate electrode formed over the depletion fin and separated therefrom by a predetermined dielectric layer, wherein the gate electrode and the dielectric layer thereunder have a predetermined configuration to assure the source and drain fins are not shorted.

## Claims

### Claim 1

A FinFET device for characterization comprising:
an active fin comprising a source fin, a depletion fin, and a drain fin;
a side fin extending from the depletion fin and coupled to a body contact for providing access for device characterization; and
a gate electrode formed over the depletion fin and separated therefrom by a predetermined dielectric layer,
wherein the gate electrode and the dielectric layer thereunder have a predetermined configuration to assure the source and drain fins are not shorted.

### Claim 2 (depends on 1)

The device of claim 1, wherein the body contact and the depletion fin are formed as one continuous piece.

### Claim 3 (depends on 1)

The device of claim 1, wherein the dielectric layer is a predetermined oxide.

### Claim 4 (depends on 1)

The device of claim 1, wherein the side fin is perpendicular to the active fin.

### Claim 5 (depends on 4)

The device of claim 4, wherein the gate electrode extends across the active fin and overlaps a portion of the side fin for ensuring that even with a slight misalignment of implant masks, the gate electrode still completely covers the depletion fin for preventing a short between the source and the drain.

### Claim 6 (depends on 1)

The device of claim 1, wherein the side fin is of a predetermined width to avoid shorting with either the source or drain fins.

### Claim 7 (depends on 1)

The device of claim 1, further comprising predetermined spacers to be formed around the active fin, the body contact, and the gate electrode.

### Claim 8 (depends on 7)

The device of claim 7, wherein the spacers are formed by annealing a lightly-doped drain implanted around the active fin, the body contact, and the gate electrode.

### Claim 9 (depends on 1)

The device of claim 1, further comprising a silicide formation alloyed into silicon surfaces of the active fin, the body contact, and the gate electrode.

### Claim 10 (depends on 1)

The device of claim 1, wherein the side fin and the body contact are implanted with a predetermined type of particles.

### Claim 11 (depends on 1)

The device of claim 1, wherein a breakdown voltage between the depletion fin and the source fin or the drain fin is at least 0.75V higher than the breakdown voltage of devices formed without contact to the body fin.

### Claim 12

A method for forming a FinFET device for characterization comprising:
forming an active fin comprising a source fin, a depletion fin, a drain fin, a side fin extending from the depletion fin, and a body contact coupled to the side fin for providing access for device characterization; and
forming a dielectric layer and a gate electrode covering the depletion fin,
wherein the gate electrode and the dielectric layer thereunder have a predetermined configuration to assure the source and drain fins are not shorted.

### Claim 13 (depends on 12)

The method of claim 12, wherein the side fin is perpendicular to the active fin.

### Claim 14 (depends on 13)

The method of claim 13, wherein the gate electrode extends across the active fin and overlaps a portion of the side fin for ensuring that even with a slight misalignment of implant masks, the gate electrode still completely covers the depletion fin for preventing a short between the source and the drain.

### Claim 15 (depends on 12)

The method of claim 12 further comprising implanting predetermined types of particles for the source fin and drain fin respectively.

### Claim 16 (depends on 15)

The method of claim 15 further comprising forming spacers around the active fin, the body contact, and the gate electrode.

### Claim 17

A FinFET device for characterization comprising:
an active fin comprising a source fin, a body fin, and a drain fin;
a first lightly-doped drain (LDD) region converting at least a portion of either the source or drain fin to be coupled with the body fin;
a body contact heavily doped with a same type of material as the LDD region and coupled with the LDD region for providing access for device characterization; and
a gate electrode formed over the body fin and separated therefrom by a predetermined dielectric layer.

### Claim 18 (depends on 17)

The device of claim 17 further comprising a second LDD region converting the source or drain fin that is not converted into the first LDD region and on an opposite side of the gate electrode.

### Claim 19 (depends on 18)

The device of claim 18 further comprising a source/drain contact heavily doped with a same type of material as the second LDD region.

### Claim 20 (depends on 17)

The device of claim 17 further comprising one or more spacers surrounding the gate electrode and above the dielectric layer.