# US 2008/0185641 A1 · Recessed transistor and method of manufacturing the same

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- Number: US 2008/0185641 A1
- Document ID: US20080185641A1
- Status: Published application
- Kind: A1
- Application number: 12/068,179
- Filed: 2008-02-04
- Published: 2008-08-07
- Earliest claimed: 2007-02-05
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Keun-Nam Kim; Makoto Yoshida; Chul Lee; Dong-Gun Park; Woun-Suck Yang
- Web page: https://patentgrep.com/patent/US20080185641A1

## CPC

- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/608: {having non-planar bodies, e.g. having recessed gate electrodes}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 64/027: {by etching at gate locations}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A recessed transistor and a method of manufacturing the same are provided. The recessed transistor may include a substrate, an active pin, a gate pattern and source and drain regions. The substrate may include an isolation layer that establishes an active region and a field region of the substrate. The substrate may include a recessed structure having an upper recess formed in the active region and a lower recess in communication with the upper recess. An active pin may be formed in a region between side surfaces of the isolation layer and the lower recess and an interface between the active region and the field region. The gate pattern may include a gate insulation layer formed on an inner surface of the recessed structure and a gate electrode formed on the gate insulation layer in the recessed structure. The source/drain regions may be formed adjacent to the active region and the gate electrode.

## Claims

### Claim 1

A recessed transistor, comprising:
an isolation layer that establishes an active region and a field region of a substrate;
a recessed structure having an upper recess on a surface portion of the active region and a lower recess in communication with the upper recess;
an active pin interposed between side surfaces of the isolation layer and the lower recess and between interfaces of the active region and the field region;
a gate insulation layer on a side surface and a bottom surface of the recessed structure;
a gate electrode on the gate insulation layer in the recessed structure; and
source and drain regions in the active region adjacent to the gate electrode.

### Claim 2 (depends on 1)

The recessed transistor of claim 1, wherein the upper recess has a first width (w1) and the lower recess has a second width (w2) less than the first width (w1).

### Claim 3 (depends on 1)

The recessed transistor of claim 1, wherein the upper recess has a side surface substantially perpendicular to an upper surface of the substrate.

### Claim 4 (depends on 1)

The recessed transistor of claim 1, wherein the isolation layer has an inclined side surface having a cross-sectional area that gradually enlarges toward an upper surface of the substrate.

### Claim 5 (depends on 1)

The recessed transistor of claim 1, wherein the isolation layer includes a first insulation layer pattern; and a second insulation layer pattern arranged under the first insulation layer pattern.

### Claim 6 (depends on 5)

The recessed transistor of claim 5, wherein the second insulation layer pattern has an inclined side surface having a cross-sectional area that gradually enlarges toward an upper surface of the substrate.

### Claim 7 (depends on 5)

The recessed transistor of claim 5, wherein a width of the first insulation layer pattern is greater than that of the second insulation layer pattern.

### Claim 8 (depends on 7)

The recessed transistor of claim 7, wherein a width of the upper recess is greater than that of the lower recess.

### Claim 9

A method of manufacturing a recessed transistor, comprising:
forming an isolation layer to establish an active region and a field region of a substrate;
forming an upper recess having a first width on a surface portion of the substrate in the active region;
partially etching the substrate exposed through the upper recess to form a recessed structure having the upper recess and a lower recess in communication with the upper recess and to form an active pin between the lower recess and the isolation layer;
forming a gate insulation layer on a side surface and a bottom surface of the recessed structure;
forming a gate electrode on the gate insulation layer in the recessed structure; and
forming source and drain regions in the active region adjacent to the gate electrode.

### Claim 10 (depends on 9)

The method of claim 9, wherein forming the upper recess includes:
forming a pad insulation layer on the substrate;
forming an insulation layer for a hard mask on the pad insulation layer;
forming a photoresist pattern on the insulation layer for the hard mask; and
partially etching the insulation layer for the hard mask, the pad insulation layer and the substrate using the photoresist pattern as an etching mask.

### Claim 11 (depends on 10)

The method of claim 10, wherein partially etching the insulation layer includes anisotropic etching.

### Claim 12 (depends on 9)

The method of claim 9, wherein partially etching the substrate exposed through the upper recess includes forming a first spacer on the side surface of the upper recess; and partially etching the substrate exposed through the lower recess using the first spacer as an etching mask.

### Claim 13 (depends on 9)

The method of claim 9, wherein forming the isolation layer includes:
forming a trench structure at the surface portion of the substrate in the field region;
forming a curing layer on a side surface and a bottom surface of the trench structure;
filling the trench structure with a field insulation layer; and
planarizing the curing layer and the field insulation layer until an upper surface of the substrate is exposed.

### Claim 14 (depends on 13)

The method of claim 13, wherein forming the trench structure includes forming the side surface of the trench structure substantially perpendicular to the upper surface of the substrate.

### Claim 15 (depends on 13)

The method of claim 13, wherein forming the trench structure includes:
anisotropically etching the substrate to form an upper trench having a side surface substantially perpendicular to the upper surface of the substrate; and
etching the substrate exposed through the upper trench to form a lower trench having a side surface substantially perpendicular to the upper surface of the substrate.

### Claim 16

A method of manufacturing a recessed transistor, comprising:
forming an upper trench having a first width at a surface portion of a substrate;
forming a lower trench having a second width less than the first width (w1), wherein the lower trench is in communication with the upper trench;
filling the upper trench and the lower trench with an isolation layer to establish an active region and a field region of the substrate;
partially etching the substrate in the active region to form a recessed structure having the upper recess and the lower recess and to form an active pin between the lower recess and the isolation layer;
forming a gate insulation layer on a side surface and a bottom surface of the recessed structure;
forming a gate electrode on the gate insulation layer in the recessed structure; and
forming source and drain regions in the active region adjacent to the gate electrode.

### Claim 17 (depends on 16)

The method of claim 16, wherein forming the upper trench includes forming a hard mask pattern on the substrate in the active region; and partially etching the substrate using the hard mask pattern as an etching mask.

### Claim 18 (depends on 16)

The method of claim 16, wherein forming the lower trench includes:
forming a first spacer on a side surface of the upper trench; and
partially etching the substrate using the first spacer as an etching mask.

### Claim 19 (depends on 18)

The method of claim 18, wherein forming the upper trench includes:
forming a pad insulation layer on the substrate;
forming an insulation layer for a hard mask on the pad insulation layer;
forming a photoresist pattern on the insulation layer for the hard mask;
partially etching the insulation layer for the hard mask, the pad insulation layer and the substrate using the photoresist pattern as an etching mask to form an insulation layer pattern for the hard mask, a pad insulation layer pattern and the upper recess;
forming a second spacer on the side surface of the upper recess; and
partially etching the substrate exposed through the upper recess using the second spacer as an etching mask to form the lower recess.