# US 2008/0185636 A1 · Semiconductor structure including doped silicon carbon liner layer and method for fabrication thereof

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- Number: US 2008/0185636 A1
- Document ID: US20080185636A1
- Status: Published application
- Kind: A1
- Application number: 11/672,109
- Filed: 2007-02-07
- Published: 2008-08-07
- Earliest claimed: 2007-02-07
- Assignees: International Business Machines Corporation
- Inventors: Zhijiong Luo; Yaocheng Liu
- Web page: https://patentgrep.com/patent/US20080185636A1

## CPC

- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/608: {having non-planar bodies, e.g. having recessed gate electrodes}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor structure and related method for fabrication thereof includes a liner layer interposed between: (1) a pedestal shaped channel region within a semiconductor substrate; and (2) a source region and a drain region within a semiconductor material layer located upon the liner layer and further laterally separated from the pedestal shaped channel region within the semiconductor substrate. The liner layer comprises an active doped silicon carbon material. The semiconductor material layer may comprises a semiconductor material other than a silicon carbon semiconductor material. The semiconductor material layer may alternatively comprise a silicon carbon semiconductor material having an opposite dopant polarity and lower carbon content in comparison with the liner layer. Due to presence of the silicon carbon material, the liner layer inhibits dopant diffusion therefrom into the pedestal shaped channel region. Electrical performance of a field effect device that uses the pedestal shaped channel region is thus enhanced.

## Claims

### Claim 1

A semiconductor structure comprising:
a semiconductor substrate having a gate electrode located over a pedestal shaped channel region within the semiconductor substrate;
a liner layer comprising an active doped silicon carbon material having a first dopant polarity and a first carbon content located upon a sidewall of the pedestal shaped channel region; and
a source region and a drain region located at least in part within a semiconductor material layer located upon the liner layer and further laterally separated from the pedestal shaped channel region.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1 wherein the semiconductor substrate comprises a bulk semiconductor substrate.

### Claim 3 (depends on 1)

The semiconductor substrate of claim 1 wherein the semiconductor substrate comprises a semiconductor-on-insulator substrate.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1 wherein the liner layer comprises an active dopant selected from the group consisting of boron, arsenic, phosphorus and indium active dopants.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1 wherein:
the pedestal shaped channel region has a curved sidewall; and
the liner layer is also located upon a floor of a recess within the semiconductor substrate adjoining the pedestal shaped channel region.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1 wherein the liner layer has:
an active dopant concentration from about 1e15 to about 1e22 dopant atoms per cubic centimeter; and
a silicon:carbon atomic ratio from about 200:1 to about 2:1.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1 wherein the semiconductor material layer comprises one of:
a semiconductor material other than a silicon carbon semiconductor material; and
a silicon carbon semiconductor material comprising a second polarity different than the first polarity and a second carbon content less than the first carbon content.

### Claim 8

A semiconductor structure comprising:
a semiconductor substrate having a gate electrode located over a pedestal shaped channel region within the semiconductor substrate;
a liner layer comprising a boron doped silicon carbon material having a first carbon content located upon a sidewall of the pedestal shaped channel region; and
a source region and a drain region located at least in part within a semiconductor material layer located upon the liner layer and further laterally separated from the pedestal shaped channel region.

### Claim 9 (depends on 8)

The semiconductor structure of claim 8 wherein the semiconductor substrate comprises a bulk semiconductor substrate.

### Claim 10 (depends on 8)

The semiconductor substrate of claim 8 wherein the semiconductor substrate comprises a semiconductor-on-insulator substrate.

### Claim 11 (depends on 8)

The semiconductor structure of claim 8 wherein:
the pedestal shaped channel region has a curved sidewall; and
the liner layer is also located upon a floor of a recess within the semiconductor substrate adjoining the pedestal shaped channel region.

### Claim 12 (depends on 8)

The semiconductor structure of claim 8 wherein the liner layer has:
a boron dopant concentration from about 1e15 to about 1e22 dopant atoms per cubic centimeter; and
a silicon:carbon atomic concentration from about 200:1 to about 2:1.

### Claim 13 (depends on 8)

The semiconductor structure of claim 8 wherein the semiconductor material layer comprises one of:
other than a silicon carbon semiconductor material; and
a silicon carbon semiconductor material having an n polarity and a second carbon content less than the first carbon content.

### Claim 14

A method for fabricating a semiconductor structure comprising:
etching a semiconductor substrate while using at least a gate electrode located over the semiconductor substrate as a mask to form a pedestal shaped channel region within the semiconductor substrate;
forming a liner layer comprising an active doped silicon carbon material adjoining a sidewall of the pedestal shaped channel region;
forming a semiconductor material layer upon the liner layer and further laterally separated from the pedestal shaped channel region; and
forming a source region and a drain region at least in part within the semiconductor material layer.

### Claim 15 (depends on 14)

The method of claim 14 wherein the etching the semiconductor substrate uses an isotropic etch to provide a curved sidewall of the pedestal shaped channel region.

### Claim 16 (depends on 14)

The method of claim 14 wherein the forming the liner layer also forms the liner layer upon a floor of a recess within the semiconductor substrate adjoining the pedestal shaped channel region.

### Claim 17 (depends on 14)

The method of claim 14 wherein the forming the liner layer and the forming the semiconductor material layer use a sequential epitaxial method.

### Claim 18 (depends on 14)

The method of claim 14 wherein the forming the source region and a drain region uses the gate electrode and at least two spacer layers as mask.

### Claim 19 (depends on 14)

The method of claim 14 further comprising forming an extension region within the semiconductor substrate.

### Claim 20 (depends on 19)

The method of claim 19 wherein the forming the extension region is undertaken both before the etching the semiconductor substrate and after the forming the semiconductor material layer.