# US 2008/0185632 A1 · Method for improving erase saturation in non-volatile memory devices and devices obtained thereof

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- Number: US 2008/0185632 A1
- Document ID: US20080185632A1
- Status: Published application
- Kind: A1
- Application number: 11/976,976
- Filed: 2007-10-29
- Published: 2008-08-07
- Earliest claimed: 2001-04-27
- Assignees: Interuniversitair Microelektronica Centrum (IMEC)
- Inventors: Bogdan Govoreanu; Maarten Rosmeulen; Pieter Blomme
- Web page: https://patentgrep.com/patent/US20080185632A1

## CPC

- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/683: {programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling}
- H10D 30/685: {from the channel}
- H10D 64/01342: {by deposition, e.g. evaporation, ALD or laser deposition (H10D64/01344 takes precedence)}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 64/037: {comprising charge-trapping insulators}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10D 64/01344: {in a nitrogen-containing ambient, e.g. N2O oxidation}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Non-volatile memory devices are disclosed. In a first example non-volatile memory device, programming and erasing of the memory device is performed through the same insulating barrier without the use of a complex symmetrical structure. In the example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to a charge storage region. Further in the example device, erasing is accomplished by tunneling positive carriers from the charge supply region to the charge storage region. In a second example non-volatile memory device, a charge storage region with spatially distributed charge storage region is included. Such a charge storage region may be implemented in the first example memory device or may be implemented in other memory devices. In the second example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to the charge storage region. In the second example device, the tunneled negative charge carriers are stored in the discrete storage sites.

## Claims

### Claim at position 1

1-26. (canceled)

### Claim 27

A non-volatile memory device comprising:
a charge supply region;
a charge storage medium;
a first insulating barrier between the charge supply region and the charge storage medium;
a control region, wherein the control region and the charge supply region are on opposite sides of the charge storage medium;
a second insulating barrier between the control region and the charge storage medium, wherein the second insulating barrier includes at least one high-k dielectric and at least one low-k dielectric, and wherein the second insulating barrier comprises:
a first portion neighboring the control region; and
a second portion neighboring the charge storage medium, wherein the first portion has on average a lower dielectric constant than the second portion.

### Claim 28 (depends on 27)

A non-volatile memory device according to claim 27, wherein the first portion of the second insulating barrier is a layer of a dielectric selected from the group consisting of a silicon oxide, a silicon nitride, and a silicon oxynitride layer.

### Claim 29 (depends on 28)

A non-volatile memory device according to claim 28, wherein the second portion of the second insulating barrier is a layer of a dielectric selected from the group consisting of: an aluminum oxides, a hafnium oxide, a hafnium silicate, HfSiON, a hafnium aluminate, and a zirconium oxide.

### Claim 30 (depends on 29)

A non-volatile memory device according to claim 29, wherein the control region is constructed of a material selected from the group consisting of a highly-doped poly-Si, a metal and a compound with metallic character.

### Claim 31 (depends on 30)

A non-volatile memory device according to claim 30, wherein the control region is constructed of a material having a work function of at least 4 eV.

### Claim 32 (depends on 27)

A non-volatile memory device according to claim 27, wherein the second portion of the second insulating barrier is a layer of a dielectric selected from the group consisting of: an aluminum oxides, a hafnium oxide, a hafnium silicate, HfSiON, a hafnium aluminate, and a zirconium oxide.

### Claim 33 (depends on 32)

A non-volatile memory device according to claim 32, wherein the second insulating barrier has a predetermined thickness selected for blocking charge carrier transfer between the control region and the charge storage medium.

### Claim 34 (depends on 27)

A non-volatile memory device according to claim 27, wherein the second insulating barrier has a predetermined thickness for blocking charge carrier transfer between the control region and the charge storage medium.

### Claim 35 (depends on 27)

A non-volatile memory device according to claim 27, wherein the control region is constructed of a material selected from the group consisting of a highly-doped poly-Si, a metal and a compound with metallic character.

### Claim 36 (depends on 35)

A non-volatile memory device according to claim 35, wherein control region is constructed of a material having a work function of at least 4 eV.

### Claim 37 (depends on 27)

A non-volatile memory device according claim 27, wherein the first insulating barrier comprises:
a first portion contacting the charge supply region, the first portion comprising at least one first tunneling dielectric; and
a second portion contacting the first portion and extending towards the charge storage medium, the second portion comprising at least one second tunneling dielectric;
wherein the first portion has on average a lower dielectric constant than the second portion, and the first portion is substantially thinner than the second portion.

### Claim 38 (depends on 37)

A non-volatile memory device according to claim 37, wherein the charge storage medium is a floating gate.

### Claim 39 (depends on 37)

A non-volatile memory device according to claim 37, wherein the charge storage medium is chosen from the group consisting of a charge trapping silicon nitride layer, a charge trapping high-k dielectric layer, a silicon-rich oxide, and a dielectric layer having small embedded conductive islands isolated from each other.

### Claim 40 (depends on 39)

A non-volatile memory device according to claim 39, wherein the charge storage medium is a dielectric layer having small embedded conductive islands isolated from each other, and the small conductive islands are made of Si or Ge nanocrystals.

### Claim 41 (depends on 27)

A non-volatile memory device according to claim 27, wherein the thickness of the second insulating barrier is selected such that, at a first electric potential applied between the control region and the charge supply region, charge carriers are transferred through the first insulating barrier and not through the second insulating barrier.

### Claim 42 (depends on 27)

A non-volatile memory device according to claim 27, wherein the second portion of the second dielectric layer consists essentially of a dielectric selected from the group consisting of Al2O3, HfO2, HfSiOx, HfSiON, HfAlOx, and ZrO2.

### Claim 43 (depends on 27)

A non-volatile memory device according to claim 27, wherein the control region is constructed of a material having work function ranging from about 4.5 eV to about 5.5 eV.

### Claim 44

A non-volatile memory device comprising:
a charge storage medium;
a first insulating barrier on a first side of the charge storage medium;
a second insulating barrier on a second side of the charge storage medium opposite the first side, the second insulating barrier comprising a low-k layer and a high-k layer, wherein the high-k layer is adjacent to the charge storage medium; and
means for applying, across the first insulating barrier, the second insulating barrier, and the charge storage medium, an electric field sufficient to induce carrier exchange across the first insulating barrier and not across the second insulating barrier.

### Claim 45 (depends on 44)

A non-volatile memory device according to claim 44, wherein the first insulating barrier comprises a low-k layer and a high-k layer, and wherein the high-k layer is adjacent to the charge storage medium.

### Claim 46

A non-volatile memory device comprising:
a channel region;
a first dielectric layer on the channel region;
a second dielectric layer on the first dielectric layer;
a charge storage medium on the second dielectric layer;
a third dielectric layer on the charge storage medium;
a fourth dielectric layer on the third dielectric layer; and
a control region on the fourth dielectric layer;
wherein an average dielectric constant of the first dielectric layer is lower than an average dielectric constant of the second dielectric layer, and an average dielectric constant of the fourth layer is lower than an average dielectric constant of the third layer.