# US 2008/0185627 A1 · RFID tag having non-volatile memory device having floating-gate fets with different source-gate and drain-gate border lengths

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- Number: US 2008/0185627 A1
- Document ID: US20080185627A1
- Status: Published application
- Kind: A1
- Application number: 12/006,330
- Filed: 2007-12-31
- Published: 2008-08-07
- Earliest claimed: 2007-02-02
- Assignees: Synopsys, Inc.
- Inventors: Andrew E. Horch
- Web page: https://patentgrep.com/patent/US20080185627A1

## CPC

- G11C 16/06: Auxiliary circuits, e.g. for writing into memory
- H10B 41/10: characterised by the top-view layout
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/685: {from the channel}
- H10D 30/6891: {characterised by the shapes, relative sizes or dispositions of the floating gate electrode}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10B 41/60: the control gate being a doped region, e.g. single-poly memory cell
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Non-volatile memory (NVM) devices are disclosed. In one aspect, a NVM device may include a substrate, and a field-effect transistor (FET). The FET may include a first doped region in the substrate and a second doped region in the substrate. The first and the second doped regions may define a channel region of the substrate between them. An insulating layer may overlie the channel region. A floating gate may overlie the insulating layer. Charge of an amount that encodes a value may be stored on the floating gate. The floating gate and the first and the second doped regions may be shaped such that the floating gate defines with the first doped region a first border of a first length, and the floating gate defines with the second doped region a second border of a second length that is less than 90% of the first length.

## Claims

### Claim 1

A radio frequency identification (RFID) tag, comprising:
an antenna; and,
a circuit having a non-volatile memory (NVM) device to store a value, comprising:
a substrate; and
a field-effect transistor (FET) including:
a first doped region in the substrate;
a second doped region in the substrate, the first and the second doped regions defining a channel region of the substrate between them;
an insulating layer over the channel region; and
a floating gate over the insulating layer to store charge of an amount that encodes the value, in which the floating gate and the first and the second doped regions are shaped such that the floating gate defines with the first doped region a first border of a first length, and the floating gate defines with the second doped region a second border of a second length that is less than 90% of the first length.

### Claim 2 (depends on 1)

The RFID tag of claim 1, in which the floating gate is not coupled with a control gate.

### Claim 3 (depends on 1)

The RFID tag of claim 1, in which the first and second doped regions are ptype.

### Claim 4 (depends on 1)

The RFID tag of claim 1, in which the first and second doped regions are ntype.

### Claim 5 (depends on 1)

The RFID tag of claim 1, in which the first doped region comprises a source region and the second doped region comprises a drain region.

### Claim 6 (depends on 1)

The RFID tag of claim 1, in which the first doped region comprises a drain region and the second doped region comprises a source region.

### Claim 7 (depends on 1)

The RFID tag of claim 1, in which a width of the second doped region at the second border is substantially equal to a width of the first doped region at the first border.

### Claim 8 (depends on 1)

The RFID tag of claim 1, in which a width of the second doped region at the second border is less than 90% of a width of the first doped region at the first border.

### Claim 9 (depends on 1)

The RFID tag of claim 1, in which the first and second borders are substantially straight.

### Claim 10 (depends on 1)

The RFID tag of claim 1, in which at least a portion of the first border is angled relative to the second border.

### Claim 11 (depends on 1)

The RFID tag of claim 1, in which the first border is substantially not straight.

### Claim 12 (depends on 1)

The RFID tag of claim 1, in which the first doped region has a portion protruding toward the second doped region.

### Claim 13 (depends on 1)

The RFID tag of claim 1, in which the first doped region has a portion receding from the second doped region.

### Claim 14 (depends on 1)

The RFID tag of claim 1, in which the second border length ranges from 20% to 85% of the first border length.

### Claim 15 (depends on 1)

The RFID tag of claim 1, in which the floating gate overlaps extension regions of the first doped region along the first border, and the floating gate overlaps extension regions of the second doped region along the second border.

### Claim 16

A method, comprising:
storing a value in a field-effect transistor (FET) of a non-volatile memory (NVM) within an RFID tag circuit by performing the following:
biasing the FET to inject electrons onto a floating gate of the FET;
differentially and capacitively drawing at least 10% more charge carriers of the floating gate toward a first doped region of the FET than toward a second doped region of the FET;
flowing charge carriers through a channel region of the FET between the first and second doped regions;
storing charge of an amount that encodes the value on the floating gate by injecting the electrons onto the floating gate of the FET while the charge carriers flow through the channel region of the biased FET.

### Claim 17 (depends on 16)

The method of claim 16, in which the electrons are injected onto the floating gate without controlling a voltage of the floating gate with a control gate.

### Claim 18 (depends on 16)

The method of claim 16, in which drawing comprises drawing the charge carriers of the floating gate toward a first border between the floating gate and the first doped region that is at least 10% longer than a second border between the floating gate and the second doped region.

### Claim 19 (depends on 18)

The method of claim 18, in which drawing the charge carriers toward the first border comprises drawing the charge carriers toward a first border that is substantially straight.

### Claim 20 (depends on 18)

The method of claim 18, in which drawing the charge carriers toward the first border comprises drawing the charge carriers toward a first border that is substantially not straight.

### Claim 21 (depends on 18)

The method of claim 18, in which drawing the charge carriers toward the first border comprises drawing the charge carriers toward a border of a portion selected from:
(1) a portion of the first doped region that protrudes towards the second doped region;
and (2) a portion of the first doped region that recedes from the second doped region.

### Claim 22 (depends on 18)

The method of claim 18, in which drawing the charge carriers toward the first border comprises drawing the charge carriers to a first border that is from 1.15 to 5 times longer than the second border.

### Claim 23 (depends on 16)

The method of claim 16, in which injecting the electrons comprises injecting the electrons by one selected from impact ionized hot-electron injection (IHEI) and channel hot-electron injection (CHEI).

### Claim 24

A method, comprising:
forming a non-volatile memory (NVM) device within an RFID tag circuit die by performing the following:
forming a field-effect transistor (FET) on a substrate, including:
forming a floating gate over a well region of a substrate; and
forming first and second doped regions in the well region on opposite sides of the floating gate including forming a first border of a first length between the first doped region and the floating gate, and forming a second border of a second length that is less than 90% of the first length between the second doped region and the floating gate; and
forming at least one selective biasing circuit on the substrate, in which the at least one selective biasing circuit is electrically coupled with the FET to apply one or more signals to the FET to store charge of an amount that encodes a value on the floating gate.

### Claim 25 (depends on 24)

The method of claim 24, in which forming the first and second borders comprises forming borders that are substantially straight.