# US 2008/0185593 A1 · Power field effect transistor and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2008/0185593 A1 - Document ID: US20080185593A1 - Status: Published application - Kind: A1 - Application number: 11/971,111 - Filed: 2008-01-08 - Published: 2008-08-07 - Earliest claimed: 2005-07-08 - Assignees: STMicroelectronics S.r.l. - Inventors: Mario Giuseppe Saggio; Ferruccio Frisina - Web page: https://patentgrep.com/patent/US20080185593A1 ## CPC - H10D 30/66: Vertical DMOS [VDMOS] FETs - H10D 12/031: {of IGBTs} - H10D 30/0291: {of vertical DMOS [VDMOS] FETs} - H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures} - H10D 62/8325: {Silicon carbide} - H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)} - H10D 64/516: {the thicknesses being non-uniform} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A method of manufacturing a vertical power MOS transistor on a wide band gap semiconductor substrate having a wide band gap superficial semiconductor layer, including the steps of forming a screening structure on the superficial semiconductor layer that leaves a plurality of areas of the superficial semiconductor layer exposed, carrying out at least a first ion implantation of a first type of dopant in the superficial semiconductor layer for forming at least one deep implanted region, carrying out at least a second ion implantation of the first type of dopant in the superficial semiconductor layer for forming at least one implanted body region of the MOS transistor aligned with the deep implanted region, carrying out at least one ion implantation of a second type of dopant in the superficial semiconductor layer for forming at least an implanted source region of the MOS transistor inside the at least one implanted body region, and a low budget activation thermal process of the first and second dopant types suitable to complete the formation of the body region, of the source region, and of the deep implanted region with diffusing the dopants in the substrate. ## Claims ### Claim 1 A method of manufacturing a vertical power MOS transistor on a wide band gap semiconductor substrate able to withstand a breakdown voltage BV higher than 600 V, and having a wide band gap superficial semiconductor layer formed on the substrate, the method comprising the steps of: forming a screening structure on said superficial semiconductor layer that leaves a plurality of areas of said superficial semiconductor layer exposed, carrying out a plurality of ion implantation steps of the first type of dopant in said superficial semiconductor substrate, through said screening structure, to form a plurality of deep implanted regions; carrying out at least a second ion implantation of the first type of dopant in said superficial semiconductor layer for forming at least one implanted body region of said MOS transistor aligned with said deep implanted regions, carrying out at least one ion implantation of a second type of dopant in said superficial semiconductor layer for forming at least an implanted source region of said MOS transistor inside said at least an implanted body region, and said method comprising an activation thermal process at temperatures lower than 1600° C. of the first type and second type of dopant suitable to complete said formation of said at least one body region, of said at least one source region and of said deep implanted regions. ### Claim 2 (depends on 1) The method according to claim 1 wherein the deeper implanted region is located at no more then 2.5 μm from the surface of said superficial semiconductor substrate. ### Claim 3 (depends on 1) The method according to claim 1 wherein each of said ion implantation steps of the first type of dopant is carried out with a growing implant energy. ### Claim 4 (depends on 1) The method according to claim 1 wherein each of said ion implantation steps of the second type of dopant is carried out with a growing implant dose. ### Claim 5 (depends on 1) The method according to claim 1 wherein at least a second ion implantation of the first type of dopant comprises at least a first implantation step for forming a first portion of said at least one implanted body region. ### Claim 6 (depends on 5) The method according to claim 5 wherein said at least a second ion implantation of the first type of dopant comprises at least a further implantation step for forming a second deeper portion with respect to said first portion of said at least one implanted body region. ### Claim 7 (depends on 5) The method according to claim 5 wherein said first ion implantation step for forming a first portion of said at least one implanted body region is formed with boron or aluminum ions with a concentration that varies in the range of 1×1013 at/cm2 and 1×1014 at/cm2 and an implant energy that varies in the range of 30 and 80 keV. ### Claim 8 (depends on 6) The method according to claim 6 wherein said at least a further implantation step is formed with boron or aluminum ions with a concentration that varies in the range of 5×1013 at/cm2 and 5×1014 at/cm2 and an implant energy that varies in the range of 300 and 500 keV. ### Claim 9 (depends on 1) The method according to claim 1 wherein said implantation steps of said first type of dopant are carried out with boron or aluminum ions, with a concentration that varies in the range of 1×1014 at/cm2 and 1×1016 at/cm2 and an implant energy in the range of 300 keV and 3 MeV. ### Claim 10 (depends on 1) The method according to claim 1, comprising forming spacers on side walls of said screening structure before carrying out said ion implantation of a second type of dopant. ### Claim 11 (depends on 10) The method according to claim 10, comprising the following steps: carrying out an etching step of said screening structure so as to reduce its dimensions and make it go back with respect to said at least one implanted body region, forming, in cascade, a thin dielectric layer and a conductive layer, and forming gate regions, by means of a conventional photolithographic technique, by etching, in succession, said conductive layer and said thin dielectric layer so that said gate regions are partially overlapped onto said at least implanted body regions insulated from said at least implanted body regions by means of said thin dielectric layer, said gate regions substantially aligned with said at least one implanted source region. ### Claim 12 (depends on 1) The method according to claim 1 wherein before carrying out said ion implantation step of the second type of dopant, a mask is formed on said superficial semiconductor layer for screening a portion of said superficial semiconductor layer. ### Claim 13 (depends on 1) The method according to claim 1 wherein said semiconductor substrate and said superficial semiconductor layer are formed by silicon carbide layers. ### Claim 14 (depends on 1) The method according to claim 1 wherein said superficial semiconductor layer is grown epitaxially. ### Claim 15 A power MOSFET device integrated on a wide band gap semiconductor substrate, able to withstand a breakdown voltage BV higher than 600 V, comprising at least an implanted body region of a first type of conductivity in said substrate, at least an implanted source region of a second type of conductivity formed inside said at least one implanted body region, a gate region projecting from said substrate and insulated therefrom by means of a dielectric layer, a plurality of deep doped regions formed in said semiconductor substrate below said implanted body region, and wherein said implanted regions are obtained only by means of successive implantation steps and an activation thermal process. ### Claim 16 (depends on 15) The power MOSFET device according to claim 15 wherein said dielectric layer comprises a first portion of a first thickness and a second portion of a second thickness lower than the first thickness, said gate region being partially overlapped onto said implanted body region and insulated therefrom by means of said second portion of said dielectric layer and substantially aligned with said at least an implanted source region formed in said at least an implanted body region. ### Claim 17 (depends on 15) The power MOSFET device according to claim 15 wherein said semiconductor substrate is of silicon carbide. ### Claim 18 (depends on 15) The power MOSFET device according to claim 15 wherein said deeper implanted region is located at no more then 2.5 μm from the surface of said superficial semiconductor substrate. ### Claim 19 A method, comprising: forming a screening structure on a wide band gap superficial semiconductor layer formed on a wide band gap semiconductor substrate to leave a plurality of exposed areas on the superficial semiconductor layer; forming a plurality of deep implanted regions in the superficial semiconductor substrate by ion implantation of a first type of dopant; forming at least one implanted body region of a MOS transistor by a second ion implantation of the first type of dopant in the superficial semiconductor layer so that at least one implanted body region is aligned with the deep implanted regions; forming at least an implanted source region inside the implanted body region by ion implantation of a second type of dopant in the superficial semiconductor layer; and applying a temperature lower than 1600° C. to the first type of dopant and the second type of dopant to complete formation of the body region, the source region, and the deep implanted region without diffusing of the first and second type of dopants in the superficial semiconductor layer and the semiconductor substrate. ### Claim 20 (depends on 19) The method of claim 19 wherein the temperature is in the range of 1400° C. to 1600° C. ### Claim 21 (depends on 20) The method of claim 20 wherein the temperature is applied for a period in the range of 15 minutes to 5 hours.