# US 2008/0185592 A1 · Semiconductor substrate with multiple crystallographic orientations

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2008/0185592 A1
- Document ID: US20080185592A1
- Status: Published application
- Kind: A1
- Application number: 11/306,713
- Filed: 2006-01-09
- Published: 2008-08-07
- Earliest claimed: 2006-01-09
- Assignees: International Business Machines Corporation
- Inventors: Byeong Y. Kim; Xiaomeng Chen; Woo-Hyeong Lee; Huilong Zhu
- Web page: https://patentgrep.com/patent/US20080185592A1

## CPC

- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/6744: {Monocrystalline silicon}
- H10D 30/6748: {having a multilayer structure or superlattice structure}
- H10D 30/6758: {characterised by the insulating substrates}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 30/798: {being provided in or under the channel regions}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/405: {Orientations of crystalline planes}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 86/01: Manufacture or treatment
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A pair of semiconductor structures and a method for fabricating a semiconductor structure each utilize a semiconductor substrate having a first crystallographic orientation, and a dielectric layer located thereupon. The method provides for epitaxially growing a semiconductor layer on the semiconductor substrate to encapsulate the dielectric layer. The method also provides for patterning the semiconductor layer to yield a semiconductor structure that comprises a bulk semiconductor structure and a semiconductor-on-insulator structure, or alternatively a patterned semiconductor layer that straddles the dielectric layer and contacts the semiconductor substrate.

## Claims

### Claim 1

A semiconductor structure comprising;
a semiconductor substrate having a first orientation;
a first semiconductor layer having the first orientation located upon and contacting the semiconductor substrate; and
a first stack layer separated from the first semiconductor layer and also upon the semiconductor substrate, the first stack layer comprising:
a first dielectric layer located over the semiconductor substrate; and
a second semiconductor layer of the first orientation located over the first dielectric layer and not contacting the semiconductor substrate.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1 further comprising a stress imparting layer located interposed between the first dielectric layer and the second semiconductor layer.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2 wherein the stress imparting layer comprises a semiconductor material.

### Claim 4 (depends on 2)

The semiconductor structure of claim 2 wherein the stress imparting layer comprises a dielectric material.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1 further comprising a second stack layer separated from the first stack layer and the first semiconductor layer and also upon the semiconductor substrate, where the second stack layer comprises:
a second dielectric layer located over the semiconductor substrate; and
a third semiconductor layer of a second orientation different from the first orientation located over the second dielectric layer and not contacting the semiconductor substrate.

### Claim 6 (depends on 5)

The semiconductor structure of claim 5 further comprising a semiconductor device located upon the first semiconductor layer, the second semiconductor layer and the third semiconductor layer.

### Claim 7

A semiconductor structure comprising;
a semiconductor substrate having a first orientation;
a first semiconductor layer having the first orientation located contacting the semiconductor substrate and straddling a first dielectric layer that also contacts the semiconductor substrate.

### Claim 8 (depends on 7)

The semiconductor structure of claim 7 further comprising a first stress imparting layer interposed between the first semiconductor layer and the first dielectric layer.

### Claim 9 (depends on 7)

The semiconductor structure of claim 7 further comprising:
a first stack layer separated from the first semiconductor layer and the first dielectric layer and also upon the semiconductor substrate, the first stack layer comprising:
a second dielectric layer located over the semiconductor substrate; and
a second semiconductor layer of the first orientation located over the second dielectric layer and not contacting the semiconductor substrate.

### Claim 10 (depends on 9)

The semiconductor structure of claim 9 further comprising a second stress imparting layer interposed between the second dielectric layer and the second semiconductor layer.

### Claim 11 (depends on 9)

The semiconductor structure of claim 9 further comprising a second stack layer separated from the first stack layer and the first semiconductor layer and also upon the semiconductor substrate, where the second stack layer comprises:
a third dielectric layer located over the semiconductor substrate; and
a third semiconductor layer of a second orientation different from the first orientation located over the third dielectric layer and not contacting the semiconductor substrate.

### Claim 12 (depends on 11)

The semiconductor structure of claim 11 wherein there is no stress imparting layer interposed between the third dielectric layer and the third semiconductor layer.

### Claim 13

A method for fabricating a semiconductor structure comprising:
providing a semiconductor substrate of a first orientation having a dielectric layer formed thereupon; and
epitaxially growing upon the semiconductor substrate an epitaxial layer that encapsulates the dielectric layer.

### Claim 14 (depends on 13)

The method of claim 13 further comprising patterning the epitaxial layer to form a patterned epitaxial layer over the dielectric layer.

### Claim 15 (depends on 14)

The method of claim 14 wherein the patterned epitaxial layer does not contact the semiconductor substrate.

### Claim 16 (depends on 14)

The method of claim 14 wherein the patterned epitaxial layer contacts the semiconductor substrate.

### Claim 17 (depends on 13)

The method of claim 13 further comprising patterning the epitaxial layer to form two patterned epitaxial layers, one contacting the semiconductor substrate and the other not contacting the semiconductor substrate.

### Claim 18 (depends on 17)

The method of claim 17 wherein the patterned epitaxial layer that contacts the semiconductor substrate also encapsulates the dielectric layer.

### Claim 19 (depends on 17)

The method of claim 17 wherein the patterned epitaxial layer that contacts the semiconductor substrate does not encapsulate the dielectric layer.

### Claim 20 (depends on 14)

The method of claim 14 further comprising forming a stress imparting layer interposed between the dielectric layer and the patterned epitaxial layer.