# US 2008/0185576 A1 · Error corrected quantum computer

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- Number: US 2008/0185576 A1
- Document ID: US20080185576A1
- Status: Published application
- Kind: A1
- Application number: 11/712,639
- Filed: 2007-03-01
- Published: 2008-08-07
- Earliest claimed: 2007-02-06
- Assignees: Qucor Pty. Ltd.
- Inventors: Lloyd Hollenberg; Ashley Stephens; Andrew Greentree; Austin Fowler; Cameron Wellard
- Web page: https://patentgrep.com/patent/US20080185576A1

## CPC

- G06N 10/70: Quantum error correction, detection or prevention, e.g. surface codes or magic state distillation
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

This invention concerns quantum error correction, that is the correction of errors in the transport and processing of qubits, by use of logical qubits made up of a plurality of physical qubits. The process takes place on a spatial array of physical qubit sites arranged with a quasi-2-dimensional topology having a first line of physical qubit sites and second line of physical qubit sites, where the first and second lines are arranged in parallel, with the sites of the first line in registration with corresponding sites in the second line. Between the first and second lines of physical qubit sites are a plurality of logic function gates, each comprised of a first physical qubit gate site associated with a first physical qubit site in the first line, and a second physical qubit gate site associated with the physical qubit site in the second line that corresponds to the first physical qubit site. The temporal process comprises the following steps: Creating a logical qubit in a section of the array by initialising an equal plurality of physical data and ancilla qubits at respective sites of the first and second lines within the section. Clocking each physical qubit site in the section at the same time. Permitting the physical data and ancilla qubits to move to an adjacent site in a clock cycle, provided that no site may contain more than one physical qubit at any time. Controlling the sites to achieve movement of ancilla qubits in the array to bring pairs of the ancilla qubits to respective first and second physical gate sites of logic function gates over the course of a number of clock cycles. Permitting logic operations to be performed at logic function gates which have both of their gate sites occupied by a physical ancilla qubit. Controlling the gate sites of the logic function gate to achieve the logic operation. Controlling the sites to achieve movement of the qubits in the array to bring pairs of all the data and ancilla qubits to respective logic function gates over the course of a number of clock cycles. Controlling the gate sites of the logic function gate to achieve the logic operation between each pair of data and ancilla qubits. Controlling the sites to achieve movement of the qubits in the array to bring all the data and ancilla qubits to respective sites where they can be read out. And, Using the values of the ancilla qubits read out to correct errors arising in the data qubits they have been gated with.

## Claims

### Claim 1

A process for performing an error corrected quantum logic function on a spatial array of physical qubit sites arranged with a quasi-2-dimensional topology having fundamental component structure comprising:
a first line of physical qubit sites and second line of physical qubit sites, where the first and second lines are arranged in parallel, with the sites of the first line in registration with corresponding sites in the second line;
between the first and second lines of physical qubit sites are a plurality of logic function gates, each comprised of a first physical qubit gate site associated with a first physical qubit site in the first line, and a second physical qubit gate site associated with the physical qubit site in the second line that corresponds to the first physical qubit site;
wherein, the temporal process comprises the following steps:
creating a logical qubit in a section of the array by initialising an equal plurality of physical data and ancilla qubits at respective sites of the first and second lines within the section;
clocking each physical qubit site in the section at the same time;
permitting the physical data and ancilla qubits to move to an adjacent site in a clock cycle, provided that no site may contain more than one physical qubit at any time;
controlling the sites to achieve movement of ancilla qubits in the array to bring pairs of the ancilla qubits to respective first and second physical gate sites of logic function gates over the course of a number of clock cycles;
permitting logic operations to be performed at logic function gates which have both of their gate sites occupied by a physical ancilla qubit;
controlling the gate sites of the logic function gate to achieve the logic operation;
controlling the sites to achieve movement of the qubits in the array to bring pairs of all the data and ancilla qubits to respective logic function gates over the course of a number of clock cycles;
controlling the gate sites of the logic function gate to achieve the logic operation between each pair of data and ancilla qubits;
controlling the sites to achieve movement of the qubits in the array to bring all the data and ancilla qubits to respective sites where they can be read out; and,
using the values of the ancilla qubits read out to correct errors arising in the data qubits they have been gated with.

### Claim 2 (depends on 1)

A process according to claim 1, wherein initialisation and readout sites are provided in the first and second lines of sites for the initialisation and readout of physical data and ancilla qubits.

### Claim 3 (depends on 1)

A process according to claim 1, wherein transport sites are provided in the first and second lines of sites and between the first and second lines of sites and gate sites.

### Claim 4 (depends on 1)

A process according to claim 1, wherein transport of physical qubit between initialisation, readout and gate sites takes place by a mechanism involving coherent transport by adiabatic passage (CTAP).

### Claim 5 (depends on 1)

A process according to claim 1, wherein transport of physical qubit between initialisation, readout and gate sites takes place by a mechanism involving coherent transport by logical SWAP operations.

### Claim 6 (depends on 1)

A process according to claim 1, wherein transport of physical qubit between initialisation, readout and gate sites takes place by a mechanism involving coherent transport by direct electric field induced transport.

### Claim 7 (depends on 1)

A process according to claim 1, wherein any one of the following logic operations is used:
CNOT,
hadamard control+CNOT,
CNOT+hadamard control,
hadamard target+CNOT+hadamard target
hadamard target+CNOT+SWAP+hadamard target
SWAP

### Claim 8 (depends on 1)

A process according to claim 1, wherein the logical qubits are constructed using a Steane code.

### Claim 9 (depends on 1)

A process according to claim 1, wherein, the qubits are realised in silicon.

### Claim 10 (depends on 9)

A process according to claim 9, wherein the qubits are realised as nuclear spin qubits, electron spin qubits or charge qubits

### Claim 11 (depends on 1)

A process according to claim 1, wherein the qubits are realised as ions in ion-traps, superconducting qubits, or electron spins in solid-state quantum dots.

### Claim 12

A fundamental component structure of a quasi-2-dimensional quantum computer architecture for performing an error corrected quantum logic function, the structure comprising:
a first line of physical qubit sites and second line of physical qubit sites, where the first and second lines are arranged in parallel, with the sites of the first line in registration with corresponding sites in the second line;
initialisation and readout sites are provided in the first and second lines of sites for the initialisation and readout of physical data and ancilla qubits;
between the first and second lines of physical qubit sites are a plurality of logic function gates, each comprised of a first physical qubit gate site associated with a first physical qubit site in the first line, and a second physical qubit gate site associated with the physical qubit site in the second line that corresponds to the first physical qubit site;
transport sites are provided in the first and second lines of sites and between the first and second lines of sites and gate sites.

### Claim 13 (depends on 12)

A structure according to claim 12, further including classical driving circuitry arranged to form regular shapes that can be combined together in a tiled arrangement.