# US 2008/0185569 A1 · Phase change random access memories including a word line formed of a metal material and methods of forming the same

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- Number: US 2008/0185569 A1
- Document ID: US20080185569A1
- Status: Published application
- Kind: A1
- Application number: 12/023,474
- Filed: 2008-01-31
- Published: 2008-08-07
- Earliest claimed: 2007-02-07
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Myung-jin Park; Young-tae Kim; Keun-ho Lee
- Web page: https://patentgrep.com/patent/US20080185569A1

## CPC

- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- H10B 63/20: {comprising selection components having two electrodes, e.g. diodes}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/8413: {adapted for resistive heating}
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A phase change memory includes a word line disposed on a semiconductor substrate and a cell diode that physically contacts the semiconductor substrate and a corresponding word line. The word line may be formed of a metal, such as tungsten. Accordingly, no metal contact is included and the word line formed of metal is in contact with the cell diode.

## Claims

### Claim 1

A phase change memory, comprising:
a word line disposed on a semiconductor substrate; and
a cell diode that physically contacts the semiconductor substrate and a corresponding word line.

### Claim 2 (depends on 1)

The phase change memory of claim 1, wherein the word line comprises a metal.

### Claim 3 (depends on 2)

The phase change memory of claim 2, wherein the metal is tungsten.

### Claim 4 (depends on 1)

The phase change memory of claim 1, wherein the semiconductor substrate is a first conductivity type semiconductor substrate, and wherein the cell diode comprises:
a low density, second conductivity type semiconductor region, which is doped to a low density; and
a high density, first conductivity type semiconductor region, which is doped to a high density and is disposed on the second conductivity type semiconductor region.

### Claim 5 (depends on 4)

The phase change memory of claim 4, wherein the first conductivity type is p-type, and the second conductivity type is n-type.

### Claim 6 (depends on 1)

The phase change memory of claim 1, wherein the cell diode is in contact with a side of the word line.

### Claim 7 (depends on 6)

The phase change memory of claim 6, wherein cell diodes disposed adjacent to each other on the same word line are defined as first and second cell diodes, wherein the first diode is in contact with a first side of the word line, and the second cell diode is in contact with a second side of the word line.

### Claim 8 (depends on 1)

The phase change memory of claim 1, wherein the word line and the cell diode are formed on the same layer.

### Claim 9 (depends on 1)

The phase change memory of claim 1, wherein the phase change memory does not comprise a metal contact.

### Claim 10 (depends on 1)

The phase change memory of claim 1, further comprising:
a phase change material disposed on the top of the cell diode; and
a bit line disposed on the top of the phase change material.

### Claim 11

A method of manufacturing a phase change memory, comprising:
forming a word line on a semiconductor substrate; and
forming a cell diode that physically contacts the semiconductor substrate and the word line.

### Claim 12 (depends on 11)

The method of claim 11, wherein the word line comprises a metal.

### Claim 13 (depends on 12)

The method of claim 12, wherein the metal is tungsten.

### Claim 14 (depends on 11)

The method of claim 11, wherein forming the word line comprises:
forming an etch stop layer on the semiconductor substrate;
forming a first interlayer insulating layer on the etch stop layer;
etching a predetermined portion of the first interlayer insulating layer; and
depositing the word line on the etched portion of the first interlayer insulating layer.

### Claim 15 (depends on 14)

The method of claim 14, further comprising:
exposing the etch stop layer using a photoresist pattern as an etching mask.

### Claim 16 (depends on 14)

The method of claim 14, wherein forming the cell diode comprises:
forming a second interlayer insulating layer on the first interlayer insulating layer;
etching a predetermined region of the first interlayer insulating layer, the second interlayer insulating layer, and the word line; and
depositing the cell diode in the etched region.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
exposing the semiconductor substrate using a photoresist pattern as an etching mask.

### Claim 18 (depends on 16)

The method of claim 16, wherein the etched region is in contact with a side of the word line.

### Claim 19 (depends on 16)

The method of claim 16, wherein in the etching the predetermined region comprises etching the predetermined region using an etching selectivity such that all materials comprising the first interlayer insulating layer, the second interlayer insulating layer, and the word line are etched.

### Claim 20 (depends on 16)

The method of claim 16, wherein the semiconductor substrate has a first conductivity type and wherein depositing the cell diode comprises:
forming a low density, second conductivity type semiconductor region, which is doped to a low density, on the semiconductor substrate; and
forming a high density, first conductivity type semiconductor region, which is doped to a high density, on the second conductivity type semiconductor region,
wherein the low density, second conductivity type semiconductor region and the high density, first conductivity type semiconductor region are formed using an epitaxial growth method.