# US 2008/0185568 A1 · Nonvolatile memory devices and method of manufacturing the same

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- Number: US 2008/0185568 A1
- Document ID: US20080185568A1
- Status: Published application
- Kind: A1
- Application number: 12/010,921
- Filed: 2008-01-31
- Published: 2008-08-07
- Earliest claimed: 2007-02-01
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Yong-wook Kwon; Chul-soon Kwon; Young-cheon Jeong
- Web page: https://patentgrep.com/patent/US20080185568A1

## CPC

- H10B 63/10: Phase change RAM [PCRAM, PRAM] devices
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 2213/79: Array wherein the access device being a transistor
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Example embodiments provide a nonvolatile memory device using resistive elements. The nonvolatile memory device may include a semiconductor substrate, a plurality of variable resistance patterns on the semiconductor substrate, and a plurality of heat sink patterns that are level with the variable resistance patterns and coupled to a ground voltage.

## Claims

### Claim 1

A nonvolatile memory device comprising:
a semiconductor substrate;
a plurality of variable resistance patterns on the semiconductor substrate; and
a plurality of heat sink patterns level with the variable resistance patterns, the heat sink patterns being coupled to a ground voltage.

### Claim 2 (depends on 1)

The nonvolatile memory device of claim 1, wherein a ground voltage line coupled to the ground voltage extends in a first direction.

### Claim 3 (depends on 2)

The nonvolatile memory device of claim 2, wherein the plurality of heat sink patterns are formed on the ground voltage line so as to extend in the first direction.

### Claim 4 (depends on 2)

The nonvolatile memory device of claim 2, wherein each of the heat sink patterns includes a first sub-heat sink pattern that is formed on the ground voltage line so as to extend in the first direction, and a second sub-heat sink pattern that extends in a second direction so as to cross the first direction.

### Claim 5 (depends on 2)

The nonvolatile memory device of claim 2, wherein the plurality of heat sink patterns include a plurality of sub-heat sink patterns that are formed on the ground voltage line so as to be spaced apart from each other in the first direction.

### Claim 6 (depends on 2)

The nonvolatile memory device of claim 2, further comprising:
spacers defining the widths of the plurality of heat sink patterns, respectively.

### Claim 7 (depends on 1)

The nonvolatile memory device of claim 1, wherein the plurality of variable resistance patterns are separately formed in memory cells.

### Claim 8

A nonvolatile memory device comprising:
a semiconductor substrate;
access transistors including gate electrodes and first and second junction regions, the gate electrodes on the semiconductor substrate, and the first and second junction regions in the semiconductor on both ends of the gate electrodes;
a ground voltage line coupled to the first junction region;
variable resistance patterns coupled to the second junction region; and
heat sink patterns coupled to the ground voltage line, the heat sink patterns being adjacent to the variable resistance patterns.

### Claim 9 (depends on 8)

The nonvolatile memory device of claim 8, wherein the heat sink patterns are level with the variable resistance patterns.

### Claim 10 (depends on 8)

The nonvolatile memory device of claim 8, wherein the ground voltage line extends in a first direction.

### Claim 11 (depends on 10)

The nonvolatile memory device of claim 10, wherein the heat sink patterns are formed on the ground voltage line so as to extend in the first direction.

### Claim 12 (depends on 10)

The nonvolatile memory device of claim 10, wherein each of the heat sink patterns includes a first sub-heat sink pattern that is formed on the ground voltage line so as to extend in the first direction, and a second sub-heat sink pattern that extends in a second direction so as to cross the first direction.

### Claim 13 (depends on 10)

The nonvolatile memory device of claim 10, wherein the heat sink patterns include a plurality of sub-heat sink patterns that are formed on the ground voltage line so as to be spaced apart from each other in the first direction.

### Claim 14 (depends on 10)

The nonvolatile memory device of claim 10, further comprising:
spacers defining the widths of the heat sink patterns, respectively.

### Claim 15 (depends on 8)

The nonvolatile memory device of claim 8, further comprising:
landing pads formed between the second junction region and the variable resistance patterns so as to be level with the ground voltage line.

### Claim 16 (depends on 15)

The nonvolatile memory device of claim 15, further comprising:
bottom electrode contacts formed between the landing pads and the variable resistance patterns.

### Claim 17 (depends on 8)

The nonvolatile memory device of claim 8, wherein the plurality of variable resistance patterns are separately formed in memory cells.

### Claim 18

A nonvolatile memory device comprising:
a semiconductor substrate;
first and second access transistors including:
first and second gate electrodes on the semiconductor substrate to extend in a first direction,
a first junction region in the semiconductor substrate between the first and second gate electrodes,
a second junction region in one side of the first gate electrode opposite to the first junction region, and
a third junction region in one side of the second gate electrode opposite to the first junction region;
a ground voltage line coupled to the first junction region, the ground voltage line extending in the first direction;
first and second variable resistance patterns coupled to the second and third junction regions, respectively; and
heat sink patterns coupled to the ground voltage line, the heat sink patterns being formed between the first and second variable resistance patterns so as to extend in the first direction.

### Claim 19 (depends on 18)

The nonvolatile memory device of claim 18, wherein the heat sink patterns are level with the first variable resistance pattern and/or the first variable resistance pattern.

### Claim 20

A method of manufacturing a nonvolatile memory device, the method comprising:
forming access transistors, which include gate electrodes formed on a semiconductor substrate and first and second junction regions formed in the semiconductor substrate on both ends of the gate electrodes;
forming a ground voltage line coupled to the first junction region and landing pads coupled to the second junction region;
forming variable resistance patterns on the landing pads; and
forming heat sink patterns on the ground voltage line so that the heat sink patterns are adjacent to the variable resistance patterns.

### Claim 21 (depends on 20)

The method of claim 20, wherein the heat sink patterns are level with the variable resistance patterns.

### Claim 22 (depends on 20)

The method of claim 20, wherein the ground voltage line extends in a first direction.

### Claim 23 (depends on 22)

The method of claim 22, wherein the heat sink patterns are formed on the ground voltage line so as to extend in the first direction.

### Claim 24 (depends on 22)

The method of claim 22, wherein each of the heat sink patterns includes a first sub-heat sink pattern that is formed on the ground voltage line so as to extend in the first direction, and a second sub-heat sink pattern that extends in a second direction so as to cross the first direction.

### Claim 25 (depends on 22)

The method of claim 22, wherein the heat sink patterns include a plurality of sub-heat sink patterns that is formed on the ground voltage line so as to be spaced apart from each other in the first direction.

### Claim 26 (depends on 22)

The method of claim 22, further comprising:
forming spacers defining the widths of the heat sink patterns, respectively.