# US 2008/0185178 A1 · Circuit board and method for manufacturing the same, semiconductor package, component built-in module and board for electronic equipment

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- Number: US 2008/0185178 A1
- Document ID: US20080185178A1
- Status: Published application
- Kind: A1
- Application number: 12/011,725
- Filed: 2008-01-29
- Published: 2008-08-07
- Earliest claimed: 2003-12-04
- Assignees: Matsushita Electric Industrial Co., Ltd.
- Inventors: Rikiya Okimoto; Yoji Ueda; Satoru Tomekawa; Tousaku Nishiyama; Shozo Ochi
- Web page: https://patentgrep.com/patent/US20080185178A1

## CPC

- H10W 70/65: Shapes or dispositions of interconnections
- H05K 1/113: {Via provided in pad; Pad over filled via}
- H05K 3/4069: {for via connections in organic insulating substrates}
- H10W 70/685: comprising multiple insulating layers
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H05K 3/4614: {the electrical connections between the circuit boards being made during lamination}
- H05K 3/4652: {Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern (H05K3/4647 takes precedence)}
- H05K 2201/0355: Metal foils
- H05K 2201/10674: Flip chip
- H05K 2203/0191: Using tape or non-metallic foil in a process, e.g. during filling of a hole with conductive paste
- H05K 2203/1461: Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/90: Bond pads, in general
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS

## Abstract

A circuit board of the present invention, includes: an electrical insulating layer including at least one layer of electrical insulating base; and a conductive portion formed in a via hole provided in the electrical insulating base. A land for mounting only is disposed on at least one surface of the electrical insulating base that is arranged at an outermost layer. According to a method for manufacturing a circuit board of the present invention, includes the steps of: forming a via hole in an electrical insulating base; filling the via hole with a conductive paste; laminating a metal foil or a releasing sheet on the electrical insulating base, and placing a jig for pressing above and below the lamination, followed by hot-pressing so as to apply heat and pressure thereto, so as to form a conductive portion made of the conductive paste in the via hole; and forming a land for mounting only on at least one surface of the electrical insulating base that is arranged at an outermost layer. Thereby, a circuit board can be provided, having a land for mounting formed with a narrow pitch.

## Claims

### Claim at position 1

1-4. (canceled)

### Claim 5

A circuit board, comprising:
an electrical insulating layer comprising at least two layers of electrical insulating base, and a conductive portion formed in a via hole provided in the electrical insulating base,
wherein the circuit board has a land for mounting disposed on at least one surface of the electrical insulating base arranged at an outermost layers,
an interlayer connection land that is electrically connected with the conductive portion, and
a wiring pattern disposed between the electrical insulating bases and connected with the interlayer connection land; and
wherein when viewing the interlayer connection land from a direction of an axis of the conductive portion, the interlayer connection land is disposed inside an outer edge of the conductive portion.

### Claim 6 (depends on 5)

The circuit board according to claim 5, wherein the wiring pattern is formed with a wiring thinner than a diameter of the conductive portion, and a part of the wiring pattern that is connected with the interlayer connection land is disposed so as to contact with the conductive portion.

### Claim 7 (depends on 6)

The circuit board according to claim 6, wherein when viewing the wiring pattern from the direction of the axis of the conductive portion, a portion of the wiring pattern that is disposed on the conductive portion has an area that is 10% or more of a cross-sectional area of the conductive portion in a radial direction.

### Claim 8 (depends on 6)

The circuit board according to claim 6, wherein when viewing the wiring pattern and the interlayer connection land from the direction of the axis of the conductive portion, a total area of a portion of the wiring pattern that is disposed on the conductive portion and an area of the interlayer connection land is 10% or more and less than 100% of a cross-sectional area of the conductive portion in a radial direction.

### Claim at position 6

9-21. (canceled)