Systems and methods for combining time division multiplexed and packet connection in a meshed switching architecture

A meshed switching circuit supporting time division multiplexed and packet connections over common links, comprising:

• a plurality of serializer/de-serializers (SerDes) configured to transmit and receive a plurality of packet and time division multiplexed connections;
• a packet interface configured to transmit and receive the plurality of packet connections to packet processing circuitry external to the circuit;
• and
• a port interface configured to transmit and receive the plurality of time division multiplexed to circuitry for time slot interchange switching;
• wherein the plurality of SerDes connect to a backplane in a mesh configuration.

A network element with a meshed backplane switching architecture supporting time division multiplexed and packet connections over common links, comprising:

• a plurality of slots connected through a backplane;
• a plurality of line cards configured to connect to the backplane each through one of the plurality of slots;
• wherein each of the plurality of line cards comprises a Fabric-Timeslot Exchanger circuit configured to:
• serialize and de-serialize a plurality of connections to the backplane, wherein the connections comprise time division multiplexed and packet connections;
• interface packet connections to an external packet processor through a system packet interface;
• frame packet connections into Generic Frame Protocol-Frame (GFP-F);
• perform time slot switching for the time division multiplexed connections;
• and
• combine the packet and time division multiplexed connections over the plurality of connections.