# US 2008/0178139 A1 · Use of breakouts in printed circuit board designs

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- Number: US 2008/0178139 A1
- Document ID: US20080178139A1
- Status: Published application
- Kind: A1
- Application number: 11/937,411
- Filed: 2007-11-08
- Published: 2008-07-24
- Earliest claimed: 2006-11-08
- Assignees: Mentor Graphics Corporation
- Inventors: Charles L. Pfeil; Henry Potts
- Web page: https://patentgrep.com/patent/US20080178139A1

## CPC

- G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347)
- H05K 1/112: {directly combined with via connections}
- H05K 3/0005: {for designing circuits by computer}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS

## Abstract

An escape outline is provided to automatically identify escape traces of a breakout. Further, the escape outline can be used to associate desired properties with the identified escape traces and allows special behavior of the automatic and interactive routing routines that operate on the escapes. Still further, an escape outline may be employed to improve the creation of escape traces by automatic routing tools. The use of pseudo-pins for netline optimization also is provided. Breakouts in a printed circuit board design are analyzed, and their respective endpoints are identified. These endpoints are then employed in a netline optimization analysis instead of the pins from which the breakouts originate. In this manner, the endpoints of the breakout are used as pseudo-pins to substitute for the actual pins of a component. Because the netline optimization will then be predicated upon the breakout endpoints rather that the originating pins, the pin configuration will be revised to simplify routing to the breakouts.

## Claims

### Claim 1

A method of swapping pins in a printed circuit board design, comprising:
identifying breakouts extending from a pin of a component object in the printed circuit board design;
for each identified breakout, identifying an endpoint of the breakout; and
providing the identified endpoints to a pin-swapping tool for use in a netline optimization process.

### Claim 2 (depends on 1)

The method recited in claim 1, wherein identifying breakouts extending from a pin of a component object in the printed circuit board design includes identifying traces that intersect a perimeter of an escape outline affiliated with the component object.

### Claim 3 (depends on 2)

The method recited in claim 2, further comprising identifying the endpoint of each breakout as an intersection of a trace of the breakout with the perimeter of an escape outline affiliated with the component object.

### Claim 4 (depends on 1)

The method recited in claim 1, further comprising:
creating a map of pins of the component object including the pseudo-pins corresponding to the breakout endpoints;
creating netlines extending from the pseudo-pins; and
performing a netline optimization process using the netlines extending from the pseudo-pins.

### Claim 5 (depends on 4)

The method recited in claim 4, further comprising:
identifying two pseudo-pins to be swapped based upon the netline optimization process using the netlines extending from the pseudo-pins; and
swapping actual pins of the component object corresponding to two identified pseudo-pins to be swapped.

### Claim 6 (depends on 28, 29, 30, 31)

A computer-readable storage medium, having a sequence of program instructions stored thereon that are executable by a computer system to perform the method of any claims 28-31.

### Claim 7

A pseudo-pin mapping tool, comprising:
a breakout identification module configured to identifying breakouts extending from a pin of a component object in the printed circuit board design; and
a breakout endpoint determination module configured to, for each identified breakout, identify an endpoint of the breakout; and
provide the identified endpoint to a pin-swapping tool for use in a netline optimization process.

### Claim 8 (depends on 7)

The pseudo-pin mapping tool recited in claim 7, further comprising:
a pin-swapping module configured to
create a map of pins of the component object using pseudo-pins corresponding to the breakout endpoints;
create netlines extending from the pseudo-pins; and
perform a netline optimization process using the netlines extending from the pseudo-pins.

### Claim 9 (depends on 8)

The pseudo-pin mapping tool recited in claim 8, wherein the pin-swapping module is further configured to
identify two pseudo-pins to be swapped based upon the netline optimization process using the netlines extending from the pseudo-pins; and
swap actual pins of the component object corresponding to two identified pseudo-pins to be swapped.