Method, Apparatus, and Computer Program Product for Implementing Balanced Wiring Delay Within an Electronic Package
OwnerGerald Keith Bartley, Darryl John Becker +4inventors
InventorsGerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
Life of this patent
Estimating the term…
Abstract
Balanced wiring delay within an electronic package is implemented. A plurality of nets in a net group is identified in the electronic package. A predefined structure is added to each net within the group. A balanced wiring delay customizing program systematically processes and reduces length of the nets until a set length balance is obtained for the net group.
Claims20
A method for implementing balanced wiring delay within an electronic package comprising the steps of:
- receiving a design file for the electronic package;
- identifying a plurality of nets in a net group in the electronic package;
- adding a predefined structure to each of said plurality of nets in said net group;
- and
- systematically processing and reducing a length of said plurality of nets in said net group until a set length balance is obtained for said net group.
A computer program product for implementing balanced wiring delay within an electronic package in a computer system, said computer program product including instructions stored on a computer readable storage medium, wherein said instructions, when executed by the computer system to cause the computer system to perform the steps of:
- receiving a design file for the electronic package;
- identifying a plurality of nets in a net group in the electronic package;
- adding a predefined structure to each of said plurality of nets in said net group;
- and
- systematically processing and reducing a length of said plurality of nets in said net group until a set length balance is obtained for said net group.
An apparatus for implementing balanced wiring delay within an electronic package comprising:
- a computer system;
- said computer system including a central processor unit (CPU) and a memory storing a balanced wiring delay customizing program and a design file for the electronic package;
- said CPU being programmed by said balanced wiring delay customizing program to perform the steps of:
- receiving said design file for the electronic package;
- identifying a plurality of nets in a net group in the electronic package;
- adding a predefined structure to each of said plurality of nets in said net group;
- and
- systematically processing and reducing a length of said plurality of nets in said net group until a set length balance is obtained for said net group.
Dependencies are inferred from the claim text.