Timing verification method and apparatus

A timing verification apparatus for obtaining delay time for a signal propagated through a signal path and performing timing verification based on the delay time, the apparatus comprising:

• a storage unit for storing a table including a wiring resistance variation amount and a wiring capacitance variation amount that are in accordance with a geometry deviation of a wire from a reference geometry;
• and
• a processing circuit for accessing the storage unit, the processing circuit:
• extracting a wiring structure of the signal path from the storage unit;
• extracting a wiring resistance variation amount and a wiring capacitance variation amount that correspond to the extracted wiring structure from the table;
• generating an on-chip-variation coefficient from the extracted wiring resistance variation amount and wiring capacitance variation amount;
• and
• calculating delay time for the signal propagated through the signal path based on the generated on-chip-variation coefficient.