US 2008/0178133 A1 · Method and Apparatus for Implementing Enhanced Timing Performance Through Bus Signal Wire Permutation With Repowering Buffers

Abstract

A method and apparatus implement improved timing performance of a signal bus through wire permutation with repowering buffers. A repowering buffer includes a prebuffer and a postbuffer. A plurality of prebuffers and postbuffers are stored in a design library, each having a set wiring ordered arrangement for selectively providing wire permutation of the signal bus. A wiring order of prebuffer at the beginning of the bus is identical to the wiring order of the postbuffer at the end of bus. The wiring order of the postbuffer driving the beginning of bus wires between adjacent repowering buffers is identical to the wiring order of the prebuffer receiving at the end of the bus wires. A wiring order of the downstream buffer pairs is chosen so that there is at least one pair of wires separated by another wire or wires in the bus.

Claims16

Dependent claims

A method for implementing improved timing performance of a signal bus through wire permutation with repowering buffers comprising the steps of:

storing a plurality prebuffers and postbuffers, each having a plurality of inverters for respectively connecting to a predefined bus wiring track, each of the stored prebuffers and postbuffers having a set wiring ordered arrangement for selectively providing wire permutation of the signal bus;
providing a selected matching wiring order for a prebuffer at the beginning of the signal bus connected to a source and a postbuffer at the end of bus connected to a sink;
said selected matching wiring order matching a driving signal bus order of the source;
and
providing an identical selected permutation wiring order of each postbuffer driving a beginning of bus wires between adjacent repowering buffers identical to a selected wiring order of the prebuffer receiving at the end of the bus wires.

2 more elements

Apparatus for implementing improved timing performance of a signal bus through wire permutation with repowering buffers comprising:

a design library storing a plurality of prebuffers and postbuffers, each having a plurality of inverters for respectively connecting to a predefined bus wiring track, each of the stored prebuffers and postbuffers having a set wiring ordered arrangement for selectively providing wire permutation of the signal bus;
a repowering buffer wire permutation design program providing a selected matching wiring order for a prebuffer at the beginning of the signal bus connected to a source and a postbuffer at the end of bus connected to a sink;
said selected matching wiring order matching a driving signal bus order of the source;
and
said repowering buffer wire permutation design program providing an identical selected permutation wiring order of each postbuffer driving a beginning of bus wires between adjacent repowering buffers identical to a selected wiring order of the prebuffer receiving at the end of the bus wires.

2 more elements

Dependencies are inferred from the claim text.

Method and Apparatus for Implementing Enhanced Timing Performance Through Bus Signal Wire Permutation With Repowering Buffers

Life of this patent

Method and Apparatus for Implementing Enhanced Timing Performance Through Bus Signal Wire Permutation With Repowering Buffers

Life of this patent

Abstract

Claims16