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US 2008/0178130 A1Published application
Fpga circuits and methods considering process variations
AssigneeThe Regents of the University of California
InventorLei He
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AssigneeThe Regents of the University of California
InventorLei He
Estimating the term…
Methods are described herein which consider both die-to-die and within-die variations in effective channel length, threshold voltage, and gate oxide thickness, based on first developing closed-form models of chip level FPGA leakage and timing variations. Execution times are significantly reduced using these methods in comparison to performing detailed evaluation. The teachings provide mean and standard deviation which were found to be within 3% from those computed by Monte Carlo simulation, while leakage and delay variations can be up to 3× and 1.9×, respectively. Analytical yield models are derived which consider both leakage and timing variations, and use such models to evaluate FPGA device and architecture in response to process variations. The teachings allow improved modeling of leakage and timing yields and thus co-optimization to improve yield rates.
A method of modeling a field programmable gate array (FPGA) subject to process variation, comprising:
A method of modeling a field programmable gate array (FPGA) subject to process variation, comprising:
A method of evaluating yield within a field programmable gate array (FPGA) subject to process variation, comprising:
Dependencies are inferred from the claim text.