Parallel optimization using independent cell instances
AssigneeProlific, Inc.
InventorsPaul de Dood, Brian Lee, Daniel Albers
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Abstract
The present invention provides a method for parallel optimization of an integrated circuit design based on the use of sets of cell instances that are independent from each other. Multiple changes to a design are analyzed in parallel by ensuring that no two cell instances that are being changed are in the same fan-in and fan-out cones. This property allows full timing analysis to be performed on a design such that multiple alternatives are explored in parallel and accurate results are obtained. By ordering the choice of cell instances to change and by ordering the alternatives to try, a greater degree of optimization is found earlier in the process.
Claims27
A method for optimizing a placed circuit design meeting a timing objective comprising the steps of:
- collecting a plurality of candidate instance cells in said design as candidates for replacement;
- identifying one or more alternative cells in a cell library for each of said plurality of candidate instance cells;
- selecting a set of selected instance cells from said plurality of candidate instance cells, wherein cells in said set of selected instance cells are independent from each other;
- replacing each of said selected instance cells with one of said one or more alternative cells;
- analyzing the timing of said placed circuit design as modified by said step of replacing.
A digital computer system programmed to optimize a placed circuit design meeting a timing objective by performing the steps of:
- collecting a plurality of candidate instance cells in said design as candidates for replacement;
- identifying one or more alternative cells in a cell library for each of said plurality of candidate instance cells;
- selecting a set of selected instance cells from said plurality of candidate instance cells, wherein cells in said set of selected instance cells are independent from each other;
- replacing each of said selected instance cells with one of said one or more alternative cells;
- analyzing the timing of said placed circuit design as modified by said step of replacing.
A computer-readable medium storing a computer program for optimizing a placed circuit design meeting a timing objective, said program implementing the steps of:
- collecting a plurality of candidate instance cells in said design as candidates for replacement;
- identifying one or more alternative cells in a cell library for each of said plurality of candidate instance cells;
- selecting a set of selected instance cells from said plurality of candidate instance cells, wherein cells in said set of selected instance cells are independent from each other;
- replacing each of said selected instance cells with one of said one or more alternative cells;
- analyzing the timing of said placed circuit design as modified by said step of replacing.
Dependencies are inferred from the claim text.