Silicon Multiple Core or Redundant Unit Optimization Tool

A system for optimization of multiple core chip design, comprising:

• a processor;
• and
• a memory coupled to the processor, the memory comprising instructions which, when executed by the processor, cause the processor to:
• define a chip design;
• break the chip design into a plurality of core entities;
• calculate the circuits in each of the plurality of core entities;
• automatically build multiple design cases with combinations of core entities;
• automatically determine a yield for each design case;
• and
• select a design case with a best yield.

A computer program product in a computer readable medium, the computer program product comprising a computer readable program which, when executed by a computing device, causes the computing device to:

• define a chip design;
• break the chip design into a plurality of core entities;
• calculate the circuits in each of the plurality of core entities;
• automatically build multiple design cases with combinations of core entities;
• automatically determine a yield for each design case;
• and
• select a design case with a best yield.