US 2008/0178060 A1Published application

Signal processing apparatus and a data recording and reproducing apparatus including local memory processor

AssigneeHitachi Global Storage Technologies Japan, Ltd.

InventorsTerumi Takashi, Seiichi Mita, Atsushi Saito

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Abstract

In a data recovery processing, the conventional overhead, primarily, latency due to a rotational recording media is removed. Secondary, in a signal processing or in a recording and reproducing apparatus, reliability of data reproduction is improved by repeatedly processing data. These processing are achieved that input signal, i.e., raw analog signal read from the recording media is digitized to be stored in a secondary storage such as a memory or a FIFO memory. The apparatus includes a signal processing circuit to repeatedly process the stored digital signal in the secondary storage. When detecting data, operation of the circuit is efficiently controlled by a change over detector parameters, in which characteristics for the detecting performance. Resultantly, data recovery processing speed is increased and reliability of data reproduced is improved.

Claims4

Dependent claims

A data demodulating apparatus, wherein a data sector stores a part of user data or the whole of the user data, and said data sector at least comprises a bit sync region for carrying out bit synchronization, a symbol sync region for carrying out symbol synchronization, a coded user data region for recording a part of said user data or the whole of the user data by coding, and an error correction detection region for error correction and error detection of the recorded data, said data demodulating apparatus comprising:

phase synchronizing means for carrying out bit synchronization in said bit synch region;
symbol synchronizing means for carrying out symbol synchronization in said symbol sync region;
and
storage means for storing a part of said bit synch region, or the whole of the region, a part of said symbol sync region, or the whole region, and data of the coded user data region, and data of said error correction detection region,
wherein, in accordance with data stored in said memory means, by utilizing said phase synchronizing means and said symbol synchronizing means, demodulation of user data or error correction detection is carried out.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/003,270Filed 21 Dec 2007
Priority: JP 10-14084722 May 1998
Published: 24 Jul 2008
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

G11B 20/10009
Digital recording or reproducing: improvement or modification of read or write signals
G11B 20/00086
Signal processing not specific to the method of recording or reproducing; Circuits therefor: circuits for prevention of unauthorised reproduction…
G11B 20/10055
Filtering or equalising, e.g. setting the tap weights of an FIR filter: using partial response filtering when writing the signal to the medium or…
G11B 20/10074
Using partial response filtering when writing the signal to the medium or reading it therefrom: ePR4, i.e. extended partial response class 4,…

Family

Application09/314,955Continuation · filed 20 May 1999
Application10/206,104Continuation · filed 29 Jul 2002
Application11/272,837Continuation · filed 15 Nov 2005
Application12/003,270Continuation
US 2003/0028820 A1Published application
US 2006/0069945 A1Published application
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From the US filing history. Foreign family members aren’t listed.