Hybrid built-in self test (bist) architecture for embedded memory arrays and an associated method

A built-in self test (BIST) architecture comprising:

• a controller adapted to operate at a lower operating frequency than a plurality of associated memory arrays;
• and
• command multipliers in communication with said controller and associated with said memory arrays,
• wherein said controller is further adapted to communicate, to said command multipliers, instructions for performing test functions on said memory arrays,
• wherein said controller further comprises a first address generator adapted to generate initial addresses for said instructions,
• wherein said command multipliers each further comprise a second address generator adapted to generate final addresses for said instructions, and
• wherein each specific command multiplier is adapted to selectively operate in one of two modes:
• a first mode, wherein said specific command multiplier is adapted to multiply said instructions so that said test functions are performed at a higher operating frequency of said specific memory array, and
• a second mode, wherein said specific command multiplier is adapted to suspend multiplication of said instructions so that said test functions are performed at said lower operating frequency.

A built-in self test (BIST) architecture comprising:

• a controller adapted to operate at a lower operating frequency than a plurality of associated memory arrays;
• command multipliers in communication with said controller and associated with said memory arrays,
• wherein said controller is further adapted to communicate, to said command multipliers, instructions for performing test functions on said memory arrays, and
• wherein each specific command multiplier is adapted to selectively operate in one of two modes:
• a first mode, wherein said specific command multiplier is adapted to multiply said instructions so that said test functions are performed at a higher operating frequency of said specific memory array, and
• a second mode, wherein said specific command multiplier is adapted to suspend multiplication of said instructions so that said test functions are performed at said lower operating frequency;
• and
• synchronization circuits adapted to provide synchronization between said command multipliers and said controller.

A built-in self test (BIST) method comprising:

• communicating, by a controller to a plurality of command multipliers, instructions for performing test functions on a plurality of memory arrays, wherein said controller operates at a lower operating frequency than said memory arrays and wherein said instructions specify one of a first mode and a second mode;
• synchronizing, by a plurality of synchronization circuits, timing between said controller and each of said command multipliers;
• and
• selectively operating, by said command multipliers, in one of said first mode and said second mode,
• wherein, for each specific command multiplier, said operating in said first mode comprises multiplying said instructions so that said test functions are performed on a specific memory array at a higher operating frequency of said specific memory array, and
• wherein, for said each specific command multiplier, said operating in said second mode comprises suspending multiplication of said instructions so that said test functions are performed on said specific memory array at said lower operating frequency.