System and method for the capture and preservation of intermediate error state data

A method for the capture and preservation of intermediate machine error state data, the method further comprising the steps of:

• associating a sub-primary error accumulation register with a primary error event register, and a secondary error event register;
• configuring the primary error event register to capture data relating to an initial error state;
• configuring the sub-primary error accumulation register to capture the identical error state data that is captured at the primary error event register;
• acquiring initial error state data at the primary error event register, and the sub-primary register.

A multiprocessor chip system having the capability to capture and preserve intermediate machine error state data, wherein the system comprises:

• a second level cache, wherein the second level cache is commonly interfaced with a primary and a secondary processing core;
• at least two primary error event registers, wherein each primary error event register is logically associated to a respective processing core;
• at least two secondary error event registers, wherein each secondary error event register is logically associated to a respective processing core;
• and
• at least two sub-primary error accumulation registers, wherein each sub-primary error accumulation register is logically associated with a respective primary error event register and a secondary error event register, and further, each sub-primary error accumulation register is configured to operate in parallel with the respective primary error event register to which the sub-primary error accumulation register is logically associated.