Computer system and power saving method thereof
AssigneeVIA Technologies, Inc.
InventorJen-Chieh Chen
Life of this patent
Estimating the term…
Abstract
A power saving method is disclosed. A halt instruction is issued to enable transition from an operational state to a power saving state. The processor broadcasts a message to a chipset. The chipset receives the sleep message and enters a power saving state, and asserts a hardware pin to disable a data bus connecting the processor and the chipset. It is determined whether a request for data transaction required during the power saving process is issued to the chipset. If the request is issued to the chipset, the chipset deasserts the hardware pin to enable the data bus, transmits the request to the processor; and, when data transaction is complete, asserts the hardware pin by the chipset to disable the data bus.
Claims17
A power saving method for a computer system, comprising:
- performing a halt instruction to enable a processor to enter a power saving state from an operational state;
- broadcasting a sleep message by the processor;
- receiving the sleep message by the chipset and entering the power saving state;
- asserting a hardware pin by the chipset to disable a data bus connecting the processor and the chipset;
- determining whether a request for data transaction required during the power saving status is issued to the chipset;
- if the request is issued to the chipset, deasserting the hardware pin by the chipset to enable the data bus;
- transmitting the request to the processor;
- and
- when data transaction is complete, asserting the hardware pin by the chipset to disable the data bus.
A computer system, comprising:
- a processor, performing a halt instruction to enter a power saving state from an operational state and broadcasting a sleep message;
- and
- a first chipset coupled to the processor, receiving the sleep message and entering the power saving state, asserting a hardware pin to disable a data bus connecting the processor, determining whether a first request for data transaction required is received during the power saving status, if the first request is received, deasserting the hardware pin to enable the data bus, and transmitting the first request to the processor, and, when data transaction is complete, asserting the hardware pin to disable the data bus.
A power saving method, comprising:
- receiving a sleep message by a chipset;
- asserting a hardware pin to disable a data bus connecting a processor and the chipset;
- deasserting the hardware pin to enable the data bus when a request for data transaction being issued to the chipset;
- transmitting the request to the processor;
- and
- asserting the hardware pin by the chipset to disable the data bus when data transaction is complete.
Dependencies are inferred from the claim text.