US 2008/0177984 A1Published application

Suppressing register renaming for conditional instructions predicted as not executed

AssigneeArm Limited

InventorsNorbert Bernard Eugene Lataille, Florent Begon, Cedric Denis Robert Airaud, Melanie Vincent

Life of this patent

Estimating the term…

Loading patent…

Abstract

Within a data processing system 2 including a register renaming mechanism 8, 22, register renaming for some conditional instructions which are predicted as not-executed is suppressed. The conditional instructions which are subject to such suppression of renaming may not be all conditional instructions, but may be those which are known to consume a particularly large number of physical registers 24 if they are subject to renaming A conditional load multiple instruction in which multiple registers are loaded with new data values taken from memory in response to signal instruction is an example where the present technique may be used, particularly when one of the registers loaded is the program counter and accordingly the instruction is a conditional branch.

Claims15

Dependent claims

Apparatus for processing data, said apparatus comprising:

a physical set of registers;
register renaming circuitry for mapping from register specifiers of an architectural set of register specifiers to registers of said physical set of registers, said architectural set of register specifiers representing registers as specified by instructions within an instruction set and said physical set of registers being physical registers for use in executing instructions of said instruction set;
prediction circuitry responsive to at least one instruction of said instruction set to be subject to mapping by said register renaming circuitry to generate a prediction for said instruction as one of:
(i) an executed prediction being a prediction that said instruction will be executed;
(ii) a not-executed prediction being a prediction that said instruction will not be executed;
renaming control circuitry responsive to a not-executed prediction for an instruction to suppress said register renaming circuitry performing a mapping for said instruction;
prediction resolving circuitry responsive to an execution outcome for said instruction to determine if said prediction is correct or is incorrect;
and
recovery circuitry responsive to said not-executed prediction for said instruction being incorrect to control said register renaming circuitry to perform said mapping for said instruction and to reverse any incorrect changes of architectural state consequent upon said not-executed prediction for said instruction being incorrect.

6 more elements

A method of processing data, said method comprising the steps of:

mapping from register specifiers of an architectural set of register specifiers to registers of a physical set of registers, said architectural set of register specifiers representing registers as specified by instructions within an instruction set and said physical set of registers being physical registers for use in executing instructions of said instruction set;
in response to at least one instruction of said instruction set to be subject to mapping, generating a prediction for said instruction as one of:
(i) an executed prediction being a prediction that said instruction will be executed;
(ii) a not-executed prediction being a prediction that said instruction will not be executed;
in response to a not-executed prediction for an instruction, suppressing performance of a mapping for said instruction;
in response to an execution outcome for said instruction, determining if said prediction is correct or is incorrect;
and
in response to said not-executed prediction for said instruction being incorrect, controlling said register renaming circuitry to perform said mapping for said instruction and reversing any incorrect changes of architectural state consequent upon said not-executed prediction for said instruction being incorrect.

5 more elements

Dependencies are inferred from the claim text.