Selective suppression of register renaming

Apparatus for processing data, said apparatus comprising:

• a physical set of registers;
• register renaming means for mapping from register specifiers of an architectural set of register specifiers to registers of said physical set of registers, said architectural set of register specifiers representing registers as specified by instructions within an instruction set and said physical set of registers being physical registers for use in executing instructions of said instruction set;
• and
• mapping control means coupled to said register renaming circuitry and responsive to a current state of said apparatus for controlling said register renaming circuit in respect of a register specifier of said architectural set of registers specifiers for an instruction either:
• (i) to suppress performance of a mapping operation thereby preserving an existing mapping from said register specifier to a register of said physical set of registers;
• or
• (ii) to generate a mapping from said register specifier to a register of said physical set of registers.

A method of processing data, said apparatus comprising the steps of:

• mapping from register specifiers of an architectural set of register specifiers to registers of a physical set of registers, said architectural set of register specifiers representing registers as specified by instructions within an instruction set and said physical set of registers being physical registers for use in executing instructions of said instruction set;
• and
• controlling said mapping in respect of a register specifier of said architectural set of registers specifiers for an instruction either:
• (i) to suppress performance of a mapping operation thereby preserving an existing mapping from said register specifier to a register of said physical set of registers;
• or
• (ii) to generate a mapping from said register specifier to a register of said physical set of registers.