Apparatus and method for decreasing the latency between instruction cache and a pipeline processor

A method for processing instructions in a pipelined processor having a series of pipelined stages which reduces latency between an instruction queue and a pipeline processor, the method comprising:

• serially fetching a plurality of instructions to be executed in said pipeline processor from a cache memory;
• decoding each of said fetched plurality of instructions in a first stage of said pipeline processor to determine if an execution branch is to be taken;
• simultaneously loading one or more of said fetched plurality of instructions into said instruction queue and into said decoder when said instruction queue and decoder are both empty;
• sequentially loading each of said fetched instructions into said instruction queue from said decoder when said instruction queue and said decoder are not empty;
• and
• shifting contents of said instruction queue to produce an instruction from said instruction queue for processing in subsequent pipeline stages.

A method for executing instructions in a pipelined processor, the method comprising:

• sequentially fetching instructions to be executed by said pipelined processor;
• determining if said fetched instructions are stored in a cache memory;
• determining whether both a decode stage of a decoder and an instruction queue stage of an instruction queue of said pipelined processor are empty;
• simultaneously loading said fetched instructions from said cache memory into said decode stage and into said instruction queue stage in parallel when both said decode stage and said instruction queue stage are empty;
• and
• sequentially reading out instructions from said instruction queue for execution in said pipelined processor.

An apparatus for reducing the latency between stages of a pipelined processor, the apparatus comprising:

• an instruction cache producing a plurality of instructions for execution by said pipelined processor;
• a plurality of decode stages connected to receive the plurality of instructions from said cache;
• an instruction queue having a plurality of locations, wherein one of the plurality of locations is configured to receive an associated instruction and a valid bit;
• and
• a multiplexer associated with said one of the plurality of locations,
• wherein, depending on a value of the valid bit, said multiplexer supplies said one of the plurality of locations in the instruction queue with either an output of one of the decode stages or an output of the instruction cache,
• wherein, when the output of the instruction cache is supplied to said one of the plurality of locations in the instruction queue, the output of the instruction cache is simultaneously supplied to said one of the decode stages,
• wherein said multiplexer receives a shift signal for said instruction queue which shifts contents of said instruction queue towards an output port of said instruction queue, and which enables said instructions from said decoder to be transferred to said instruction queue,
• wherein said output port of said instruction queue is connected to a plurality of parallel processing stages, and
• wherein said processing stages execute instructions belonging to one of a load/store operation, an arithmetic operation, or a branch target instruction.