Random stimuli generation of memory maps and memory allocations

Apparatus for verification of a hardware design, comprising:

• a CSP solver, which is arranged to solve constraint satisfaction problems (CSP);
• and
• a processor, which is arranged to accept definitions of requests to allocate regions in a memory of the hardware design, such that at least two of the requests are specified independently of one another, the requests indicating respective allocation types, to accept a specification of overlap restrictions between at least some of the allocation types, to automatically convert the requests and the overlap restrictions to a CSP formula, which comprises CSP constraints based on the requests, the allocation types and the overlap restrictions, to invoke the CSP solver to produce a solution of the CSP formula, to produce responsively to the solution a random test program, which comprises a memory map that allocates the regions in the memory while complying with the requests and the overlap restrictions, and to apply the test program to the hardware design.

A computer software product for verification of a hardware design, the product comprising a computer-readable medium, in which program instructions are stored, which instructions, when read by a computer, cause the computer to accept definitions of requests to allocate regions in a memory of the hardware design, such that at least two of the requests are specified independently of one another, the requests indicating respective allocation types, to accept a specification of overlap restrictions between at least some of the allocation types, to automatically convert the requests and the overlap restrictions to a constrain satisfaction problem (CSP), which comprises CSP constraints based on the requests, the allocation types and the overlap restrictions, to solve the CSP formula to produce a random test program, which comprises a memory map that allocates the regions in the memory while complying with the requests and the overlap restrictions, and to apply the test program to the hardware design.