Design Stucture for Multi-Level Memory Architecture With Data Prioritization
AssigneeInternational Business Machines Corporation
InventorsGerald K. Bartley, John M. Borkenhagen, Philip R. Germann, William P. Hovis
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Abstract
A design structure for controlling computer-readable memory includes a plurality of memory locations, a usage frequency of a data unit stored in a first memory location is determined. The data unit is moved to a second memory location, different from the first memory location that is selected based on a correspondence between a known latency of the second memory location and the usage frequency of the data unit, in which the second memory location is the primary data storage location for the data unit.
Claims6
A design structure embodied in a machine readable medium, the design structure comprising:
- a. a plurality of memory locations, each memory location having a known latency that is classified into one of a plurality of latency classes;
- b. a usage frequency indicator associated with each of the memory locations;
- c. an incrementer that increments each usage frequency indicator each time a data unit stored in a corresponding memory location is accessed over a predetermined number of cycles;
- and
- d. a memory controller that stores each data unit in a primary memory location that is a member of a latency class corresponding to a usage frequency of the data unit.
Dependencies are inferred from the claim text.