Method and system for using dynamic random access memory as cache memory
AssigneeMicron Technology, Inc.
InventorsBrent Keeth, Brian M. Shirley, Charles H. Dennison, Kevin J. Ryan
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AssigneeMicron Technology, Inc.
InventorsBrent Keeth, Brian M. Shirley, Charles H. Dennison, Kevin J. Ryan
Estimating the term…
A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.
1-27. (canceled)
A method of caching memory in a processor-based system, comprising:
A method of storing data, comprising:
A method of storing data in a first memory having a plurality of locations, at least some of which may be inaccessible at times, the method comprising:
Dependencies are inferred from the claim text.