Defective memory block remapping method and system, and memory device and processor-based system using same

A method of addressing a memory device having blocks of non-volatile memory cells, the method comprising:

• keeping a record of the respective block addresses of all blocks of memory cells in the memory device that are non-functional;
• receiving a block address corresponding to a block of the memory cells;
• providing an output block address corresponding to the sum of the received block address and the sum of addresses corresponding to the sizes of any and all non-functional blocks of memory cells having respective block addresses in the kept record that are lower than or equal to the output block address;
• and
• using the output block address to address the memory device.

A block remapping system for a non-volatile memory device having memory cells arranged in blocks each of which is associated with a respective block address, the system comprising:

• a storage device containing a record of the address of each block of memory cells that is non-functional;
• a first comparator coupled to the storage device, the first comparator being configured to compare a received block address with at least some of the block addresses contained in the storage device, the first comparator being operable to compare the received block address with the block addresses contained in the storage device in order from a lowest address to a highest address;
• a first adder coupled to receive the received block address and being operable to receive a block size value corresponding to the size of each non-functional block having a respective address contained in the storage device, the first adder being configured to add to the received block address the block size value corresponding to any block having a block address found by the first comparator to be smaller than or equal to the received block address;
• an output device coupled to the first adder and being configured to provide as an output block address the block addresses added by the adder.

A block remapping system for a non-volatile memory device having memory cells arranged in blocks each of which is associated with a respective block address, the system comprising:

• a storage device containing a record of the block address and a block size value for each block of memory cells that is non-functional, each of the block address contained in the storage device being associated with a respective index value, the index numbers being assigned to the block addresses in order from a lowest index number associated with a lowest block address to a highest index number associated with a highest block address;
• a counter coupled to the storage device and being configured to provide the index numbers to the storage device responsive to being incremented;
• a first comparator coupled to receive the index values from the counter and being operable to generate a first comparison signal responsive to determining that the index value is an initial index value;
• a first multiplexer having a first input coupled to receive an input block address and a second input coupled to receive an output block address, the first multiplexer being configured to output the input block address responsive to the first comparison signal and to otherwise output the output block address;
• an adder coupled to the storage device and the output of the first multiplexer, the adder being configured to generate a sum address corresponding to the sum of the block address at the output of the first multiplexer and a block size value received from the storage device;
• a second comparator coupled to receive the block address at the output of the first multiplexer and the block address from the storage device and being operable to generate a second comparison signal responsive to determining that the block address at the output of the first multiplexer is less than a block address received from the storage device;
• and
• a second multiplexer having a first input coupled to receive the sum address from the adder and a second input coupled to the output of the first multiplexer, the second multiplexer being configured to output as the output block address the block address at the output of the first multiplexer responsive to the second comparison signal and to otherwise output the sum address.

A non-volatile memory device, comprising:

• a signal bus;
• a bus interface operable to receive signals from the signal bus indicative of a memory command and a memory address, the bus interface further being operable to receive signals from the signal bus corresponding to write data and to output signals to the signal bus indicative of read data;
• an array of non-volatile memory cells arranged in blocks each of which is associated with a respective block address;
• a control logic unit coupled to the bus interface and the array of non-volatile memory cells, the control logic being operable to carry out operations in the array corresponding to a memory command at a location in the array corresponding to a memory address;
• a storage device containing a record of the address of each block of memory cells that is non-functional;
• a first comparator coupled to the storage device, the first comparator being configured to compare a received block address with at least some of the block addresses contained in the storage device, the first comparator being operable to compare the received block address with the block addresses contained in the storage device in order from a lowest address to a highest address;
• a first adder coupled to receive the received block address and being operable to receive a block size value corresponding to the size of each non-functional block having a respective address contained in the storage device, the first adder being configured to add to the received block address the block size value corresponding to any block having a block address found by the first comparator to be smaller than or equal to the received block address;
• an output device coupled to the first adder and being configured to provide as an output block address the block addresses added by the adder.

A non-volatile memory device, comprising:

• a signal bus;
• a bus interface operable to receive signals from the signal bus indicative of a memory command and a memory address, the bus interface further being operable to receive signals from the signal bus corresponding to write data and to output signals to the signal bus indicative of read data;
• an array of non-volatile memory cells arranged in blocks each of which is associated with a respective block address;
• a control logic unit coupled to the bus interface and the array of non-volatile memory cells, the control logic being operable to carry out operations in the array corresponding to a memory command at a location in the array corresponding to a memory address;
• a block remapping system, the system comprising:
• a storage device containing a record of the block address and a block size value for each block of memory cells that is non-functional, each of the block address contained in the storage device being associated with a respective index value, the index numbers being assigned to the block addresses in order from a lowest index number associated with a lowest block address to a highest index number associated with a highest block address;
• a counter coupled to the storage device and being configured to provide the index numbers to the storage device responsive to being incremented;
• a first comparator coupled to receive the index values from the counter and being operable to generate a first comparison signal responsive to determining that the index value is an initial index value;
• a first multiplexer having a first input coupled to receive an input block address and a second input coupled to receive an output block address, the first multiplexer being configured to output the input block address responsive to the first comparison signal and to otherwise output the output block address;
• an adder coupled to the storage device and the output of the first multiplexer, the adder being configured to generate a sum address corresponding to the sum of the block address at the output of the first multiplexer and a block size value received from the storage device;
• a second comparator coupled to receive the block address at the output of the first multiplexer and the block address from the storage device and being operable to generate a second comparison signal responsive to determining that the block address at the output of the first multiplexer is less than a block address received from the storage device;
• and
• a second multiplexer having a first input coupled to receive the sum address from the adder and a second input coupled to the output of the first multiplexer, the second multiplexer being configured to output as the output block address the block address at the output of the first multiplexer responsive to the second comparison signal and to otherwise output the sum address.

A processor-based system, comprising:

• a processor operable to process data and to provide memory commands and addresses;
• an input device coupled to the processor;
• an output device coupled to the processor;
• and
• a non-volatile memory device, comprising:
• a signal bus;
• a bus interface operable to receive signals from the signal bus indicative of a memory command and a memory address, the bus interface further being operable to receive signals from the signal bus corresponding to write data and to output signals to the signal bus indicative of read data;
• an array of non-volatile memory cells arranged in blocks each of which is associated with a respective block address;
• a control logic unit coupled to the bus interface and the array of non-volatile memory cells, the control logic being operable to carry out operations in the array corresponding to a memory command at a location in the array corresponding to a memory address;
• a storage device containing a record of the address of each block of memory cells that is non-functional;
• a first comparator coupled to the storage device, the first comparator being configured to compare a received block address with at least some of the block addresses contained in the storage device, the first comparator being operable to compare the received block address with the block addresses contained in the storage device in order from a lowest address to a highest address;
• a first adder coupled to receive the received block address and being operable to receive a block size value corresponding to the size of each non-functional block having a respective address contained in the storage device, the first adder being configured to add to the received block address the block size value corresponding to any block having a block address found by the first comparator to be smaller than or equal to the received block address;
• an output device coupled to the first adder and being configured to provide as an output block address the block addresses added by the adder.

A processor-based system, comprising:

• a processor operable to process data and to provide memory commands and addresses;
• an input device coupled to the processor;
• an output device coupled to the processor;
• and
• a non-volatile memory device, comprising:
• a signal bus;
• a bus interface operable to receive signals from the signal bus indicative of a memory command and a memory address, the bus interface further being operable to receive signals from the signal bus corresponding to write data and to output signals to the signal bus indicative of read data;
• an array of non-volatile memory cells arranged in blocks each of which is associated with a respective block address;
• a control logic unit coupled to the bus interface and the array of non-volatile memory cells, the control logic being operable to carry out operations in the array corresponding to a memory command at a location in the array corresponding to a memory address;
• a block remapping system, the system comprising:
• a storage device containing a record of the block address and a block size value for each block of memory cells that is non-functional, each of the block address contained in the storage device being associated with a respective index value, the index numbers being assigned to the block addresses in order from a lowest index number associated with a lowest block address to a highest index number associated with a highest block address;
• a counter coupled to the storage device and being configured to provide the index numbers to the storage device responsive to being incremented;
• a first comparator coupled to receive the index values from the counter and being operable to generate a first comparison signal responsive to determining that the index value is an initial index value;
• a first multiplexer having a first input coupled to receive an input block address and a second input coupled to receive an output block address, the first multiplexer being configured to output the input block address responsive to the first comparison signal and to otherwise output the output block address;
• an adder coupled to the storage device and the output of the first multiplexer, the adder being configured to generate a sum address corresponding to the sum of the block address at the output of the first multiplexer and a block size value received from the storage device;
• a second comparator coupled to receive the block address at the output of the first multiplexer and the block address from the storage device and being operable to generate a second comparison signal responsive to determining that the block address at the output of the first multiplexer is less than a block address received from the storage device;
• and
• a second multiplexer having a first input coupled to receive the sum address from the adder and a second input coupled to the output of the first multiplexer, the second multiplexer being configured to output as the output block address the block address at the output of the first multiplexer responsive to the second comparison signal and to otherwise output the sum address.