US 2008/0177930 A1 · FULLY ASSOCIATIVE BANKING FOR MEMORY

Abstract

A system is provided that facilitates read access in a memory device. The system comprises a plurality of row addresses buffers that store high order addresses associated with one or more software threads. The system further comprises a plurality of row data buffers. The row data buffers are each associated with at least one row address buffer and store row data within the range of the high order addresses of the row address buffers. The system increase memory device performance by limiting the latency associated with context switching. The plurality of row address buffers and row data buffers enables software threads to associate with one or more buffers and maintain efficient subsequent memory accesses despite context switching.

Claims20

Dependent claims

A memory system that facilitates read accesses in a memory device comprising:

a plurality of row address buffers that store high order addresses of a memory array;
and
a plurality of row data buffers, a row data buffer among the plurality of row data buffers stores memory array data corresponding to a lower order address and a high order address stored in a row address buffer among the plurality of row address buffers,
each row address buffer of the plurality of row address buffers is individually one of freely associated with or paired with at least one row data buffer of the plurality of row data buffers.

1 more element

Dependencies are inferred from the claim text.

Fully associative banking for memory

Life of this patent

Fully associative banking for memory

Life of this patent

Abstract

Claims20