Semiconductor memory device which includes memory cell having charge accumulation layer and control gate

A semiconductor memory device having a first operation mode in which an operation is automatically carried out under a control of a processor and a second operation mode in which the operation is carried out independently of the control of the processor, comprising:

• a memory cell array which includes a nonvolatile memory cell;
• a power source circuit which generates a voltage to be used in at least any one of write, erase and read of data with respect to the memory cell;
• the processor which generates a first signal on the first operation mode to control an operation of the power source circuit;
• and
• a control circuit which includes a first register configured to hold one of the first signal and a second signal and which controls the power source circuit based on one of the first and second signals held in the first register, the second signal being a signal to boot the power source circuit, the first register holding the first signal after holding the second signal when the second operation mode is changed to the first operation mode.

A semiconductor memory device in which an operation is automatically carried out under a control of a processor, comprising:

• a first memory block including a plurality of nonvolatile memory cells, data held in the memory cells included in the first memory block being erased at a time.
• a plurality of second memory blocks including the memory cells, data held in the memory cells included in the second memory blocks being erase at a time, the number of the memory cells included in each of the second memory blocks being smaller than that in the first memory block;
• a sense amplifier which reads data from the memory cell and amplifies the data, the sense amplifier reading data from selected one of the second memory block and non-selected one of the second memory blocks continuously, when the data is read from one of the second memory block;
• a verification circuit which verifies whether or not write or erase of data to the memory cell has been carried out properly using the data read by the sense amplifier, the verification circuit, when the data is read from the non-selected one of the second memory cell block, determining that the write or erase of data has been performed properly regardless of the read data;
• and
• the processor which provides information concerning selection/non-selection of the second memory block to the verification circuit.