Memory system and method having volatile and non-volatile memory devices at same hierarchical level
AssigneeMicron Technology, Inc.
InventorDean A. Klein
Life of this patent
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AssigneeMicron Technology, Inc.
InventorDean A. Klein
Estimating the term…
A processor-based system includes a processor coupled to core logic through a processor bus. This includes a dynamic random access memory (“DRAM”) memory buffer controller. The DRAM memory buffer controller is coupled through a memory bus to a plurality of a dynamic random access memory (“DRAM”) modules and a flash memory module, which are at the same hierarchical level from the processor. Each of the DRAM modules includes a memory buffer to the memory bus and to a plurality of dynamic random access memory devices. The flash memory module includes a flash memory buffer coupled to the memory bus and to at least one flash memory device. The flash memory buffer includes a DRAM-to-flash memory converter operable to convert the DRAM memory requests to flash memory requests, which are then applied to the flash memory device.
A processor-based system, comprising:
A non-volatile memory module, comprising:
A non-volatile memory buffer, comprising:
In a processor-based system, a method of transferring data from a non-volatile memory device to a dynamic random access memory (“DRAM”) device, comprising:
Dependencies are inferred from the claim text.