Method and apparatus for controlling timing of state transition of serial data line in 12c controller

A method of controlling the timing of a state transition of a serial data line (SDA) in an I2C controller, the method comprising:

• detecting a falling edge of a clock signal of a serial clock line (SCL);
• counting a hold time of the state transition of the SDA if the falling edge of the clock signal of the SCL is detected;
• and
• transmitting the state of the SDA if the count of the hold time is finished.

A computer-readable recording medium storing a program for executing a method of controlling the timing of a state transition of a serial data line (SDA) in an I2C controller, the method comprising:

• detecting a falling edge of a clock signal of a serial clock line (SCL);
• counting a hold time of the state transition of the SDA if the falling edge of the clock signal of the SCL is detected;
• and
• transmitting the state of the SDA if the count of the hold time is finished.

An I2C controller for controlling the timing of a state transition of a serial data line (SDA), the I2C controller comprising:

• a serial clock line SCL edge detector which detects an edge of a clock signal of an SCL;
• a counter which counts a hold time of the state transition of the SDA when a falling edge of the clock signal of the SCL is detected by the SCL edge detector;
• an SDA generator which transits a state of the SDA if the count of the hold time is finished;
• and
• a processor which interfaces the SCL edge detector, the counter, and the SDA generator.

A system-on-chip which controls the timing of a state transition of a serial data line (SDA), the system-on-chip comprising:

• a serial clock line SCL edge detector which detects an edge of a clock signal of an SCL;
• a counter which counts a hold time of the state transition of the SDA when a falling edge of the clock signal of the SCL is detected by the SCL edge detector;
• an SDA generator which transits a state of the SDA if the count of the hold time is finished;
• and
• a processor which interfaces the SCL edge detector, the counter, and the SDA generator.