Serial Concatenated Convolutional Code Decoder

The serial concatenated convolutional code decoder according to claim 8, wherein each of said plurality of codeblock segments is comprised of at least one overlap bit portion and a non-overlap bit portion, said overlap bit portion comprising soft-decision bits included within two or more codeblock segments of said plurality of codeblock segments, and said non-overlap bits portion comprising soft-decision bits included within a single codeblock segment of said plurality of codeblock segments.

The serial concatenated convolutional code decoder according to claim 8, wherein each of said plurality of inner decoding engines is configured for concurrently processing one of said plurality of codeblock segments.

A serial concatenated convolutional code decoder, comprising:

• at least one processing loop module comprising a permutation module, an inner decoder module, a depermutation module, and an outer decoder module;
• and
• wherein said inner decoder module is subdivided into a plurality of inner decoding engines configured for concurrently performing a decoding operation based on an inner convolutional code, said outer decoder module is subdivided into a plurality of outer decoding engines configured for concurrently performing a decoding operation based on an outer convolutional code, and at least one of said inner convolutional code and said outer convolutional code is designed in accordance with a maximum aposteriori probability based decoding algorithm.