US 2008/0177517 A1Published application

Techniques for calculating circuit block delay and transition times including transistor gate capacitance loading effects

OwnerBarry Lee Dorfman, Thomas Edward Rosser +1inventors

InventorsBarry Lee Dorfman, Thomas Edward Rosser, Jeffrey Paul Soreff

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Abstract

Techniques for modeling delay and transition times of logical circuit blocks including transistor gate capacitance loading effects provides improved simulation of logical circuit block transition times and delay times. The non-linear behavior of transistor gates of other logical circuit block inputs that are connected to the logical circuit block output is taken into account by a transition time function and a delay time function that are each separately dependent on static capacitance and transistor gate capacitance and can be used to determine logical circuit block timing and output performance. A separate N-channel and P-channel gate capacitance may also be used as inputs to the transition time and delay time functions to provide further improvement, or a ratio of N-channel to P-channel capacitances may alternatively be used as input to the transition time and delay time functions.

Claims15

Dependent claims

A method for modeling, in a computer system, the behavior of a logical circuit block, the method comprising:

first calculating in said computer system a transition time of said logical circuit block as a first mathematical function of a transistor gate capacitance of one or more logical circuit inputs connected to an output of said logical circuit block and a static load capacitance value, wherein said first mathematical function is separately dependent on said transistor gate capacitance and said static load capacitance value;
second calculating in said computer system a delay time of said logical circuit block as a second mathematical function of said transistor gate capacitance and said static load capacitance value, wherein said second mathematical function is separately dependent on said transistor gate capacitance and said static load capacitance value, and wherein coefficients of said first and second mathematical functions with respect to said transistor gate capacitance are determined in conformity with a variation of said transistor gate capacitance with respect to transistor gate voltage;
and
displaying by said computer system, a result of at least one of said first and second calculating.

1 more element

A workstation computer system including a memory for storing program instructions and data, and a processor for executing said program instructions, and wherein said program instructions comprise program instructions for:

first calculating a transition time of said logical circuit block as a first mathematical function of a transistor gate capacitance of one or more logical circuit inputs connected to an output of said logical circuit block and a static load capacitance value, wherein said first mathematical function is separately dependent on said transistor gate capacitance and said static load capacitance value,
second calculating delay time of said logical circuit block as a second mathematical function of said transistor gate capacitance and said static load capacitance value, wherein said second mathematical function is separately dependent on said transistor gate capacitance and said static load capacitance value, and wherein coefficients of said first and second mathematical functions with respect to said transistor gate capacitance are determined in conformity with a variation of said transistor gate capacitance with respect to transistor gate voltage, and
displaying a result of at least one of said first and second calculating.

A computer program product comprising a computer-readable storage medium encoding program instructions and data for execution on a general-purpose computer system, wherein said program instructions comprise program instructions for:

first calculating a transition time of said logical circuit block as a first mathematical function of a transistor gate capacitance of one or more logical circuit inputs connected to an output of said logical circuit block and a static load capacitance value, wherein said first mathematical function is separately dependent on said transistor gate capacitance and said static load capacitance value,
second calculating delay time of said logical circuit block as a second mathematical function of said transistor gate capacitance and said static load capacitance value, wherein said second mathematical function is separately dependent on said transistor gate capacitance and said static load capacitance value, and wherein coefficients of said first and second mathematical functions with respect to said transistor gate capacitance are determined in conformity with a variation of said transistor gate capacitance with respect to transistor gate voltage, and
displaying a result of at least one of said first and second calculating.

Dependencies are inferred from the claim text.