US 2008/0177514 A1 · METHOD FOR MODELING VARACTOR BY DIRECT EXTRACTION OF PARAMETERS

Abstract

A method for modeling a varactor with a MOS structure, and transforms an s-parameter obtained by the measurement using measurement equipment into a y-parameter and a z-parameter and then directly extracts parameters required for the modeling by means of equations in accordance with embodiments. The modeling can be made reflecting the parameters of the varactor varied according to frequency so that the more accurate RF modeling of a passive device can be made and the accurate modeling of the varactor can be made through the direct extraction method of the parameters so that the parameters of the varactor having a physical meaning can be extracted without using an expensive CAD tool, the time required for optimizing the parameters can be reduced, a computing time can be shorten, an initial condition dependence generated in performing the optimization is not required, and a pattern for a test is not required.

Claims20

Dependent claims

A method comprising:

providing MOS varactor including a gate, a source, and a drain formed over a p-type semiconductor substrate,
calculating a first port gate impedance ZA, a second port bulk impedance ZB and a substrate impedance ZC in a measured s-parameter using a first model equation
Re(ZA)=Re(Z11−Z12)=Rgate
and a second model equation
Im

(
Z
A
)
=
Im

(
Z
11
-
Z
12
)
=
ω


L
gate
-
1
ω


C
var
,
where Lgate represents, Rgate represents a unit cell via/contact resistance of the first port and the gate, and Cvar is formed of Cgate and Cpar, where Cgate represents a variable capacity of a MOS-type variable capacitance and Cpar represents a parasitic capacitance of the varactor, parameters Z11 and Z12 are values obtained by transforming the measured s-parameter, and ω is a constant.

32 more elements

A method for modeling a MOS varactor including a gate, a source, and a drain formed over a p-type semiconductor substrate, the varactor having parameters including a first port gate impedance ZA and a second port bulk impedance ZB, a substrate impedance ZC, a parameter Rgate representing a unit cell via/contact resistance of the first port and the gate that are directly extracted from the following model equations;

Re

(
Z
A
)
=
Re

(
Z
11
-
Z
12
)
=
R
gate
,
and
Im
(
Z
A
)
=

Im

(
Z
11
-
Z
12
)
=
ω


L
gate
-
1
ω


C
var
,
where Lgate represents the overall inductance of the first port via and the gate, Rgate represents the unit cell via/contact resistance of the first port and the gate, Cpar represents a parasitic capacitance of the varactor, Cgate represents a variable capacity of variable capacitance, Rsd represents a unit cell via/contact resistance of the second port and a bulk terminal, Lsd represents an overall inductance of the second port via and the bulk terminal, Dnwpsub represents a diode existing between an N-well and the p-type semiconductor substrate, Rsub represents a resistance of the p-type semiconductor substrate, and Csub represents a capacitance of the p-type semiconductor substrate.

49 more elements

Dependencies are inferred from the claim text.

Method for modeling varactor by direct extraction of parameters

Life of this patent

Method for modeling varactor by direct extraction of parameters

Life of this patent

Abstract

Claims20