Method and system for testing processor cores

A method for manufacturing yield testing and configuring a multi-core processor system chip comprising a plurality of processing cores, comprising:

• setting at least one adjustable power supply component to provide a supply voltage having an initial nominal supply voltage value to each of the plurality of processing cores, the initial nominal supply voltage value specified as operating a processing core at a minimum reference clock speed pursuant to a design rule;
• for N iterations selecting a core of the plurality of processing cores and iteratively lowering a core set supply voltage provided by the at least one adjustable power supply component to the selected core and observing a clock speed of the selected core at the lowered supply voltage until an Nth observed clock speed generated responsive to an Nth lowered supply voltage is less than the minimum reference clock speed and setting the at least one adjustable power supply component to provide an (N-1)th lowered supply voltage as an operative supply voltage to the selected core;
• repeating the N iteration core selecting, the iterative supply voltage lowering and clock speed observing and the (N-1)th lowered supply voltage operative supply voltage setting for each unselected core of the processing core plurality until each of the cores has been selected, wherein different cores may have different core operative supply voltages set relative to the minimum reference clock speed;
• determining an overall power consumption value for the multi-core processor system with each of the plurality of cores operating at its respective set operative supply voltage;
• and
• passing the multi-core processor system chip if the overall power consumption value does not exceed a specified maximum power consumption value;
• or
• failing the chip.

A method for manufacturing yield testing and configuring a plurality of processing cores, the method comprising:

• producing computer executable program code;
• storing the code on a computer readable medium;
• and
• providing the program code to be deployed and executed on a computer system;
• the program code comprising instructions which, when executed on the computer system, cause the computer system to test and configure a multi-core processor system chip comprising a plurality of processing cores by:
• setting at least one adjustable power supply component to provide a supply voltage having an initial nominal supply voltage value to each of the plurality of processing cores, the initial nominal supply voltage value specified to operate a processing core at a minimum reference clock speed pursuant to a design rule;
• for N iterations selecting a core of the plurality of processing cores and iteratively lowering a care set supply voltage provided by the at least one adjustable power supply component to the selected core and observing a clock speed of the selected core at the lowered supply voltage until an Nth observed clock speed generated responsive to an Nth lowered supply voltage is less than the minimum reference clock speed and setting the at least one adjustable power supply component to provide an (N-1)th lowered supply voltage as an operative supply voltage to the selected core;
• repeating the N iteration core selecting, the iterative supply voltage lowering and clock speed observing and the (N-1)th lowered supply voltage operative supply voltage setting for each unselected core of the processing core plurality until each of the cores has been selected, wherein different corps may have different core operative supply voltages set relative to the minimum reference clock speed;
• determining an overall power consumption value for the multi-core processor system with each of the plurality of cores operating at its respective set operative supply voltage;
• and
• passing the multi-core processor system chip if the overall power consumption value does not exceed a specified maximum power consumption value;
• or
• failing the chip.

A method for deploying an application for manufacturing yield testing and configuring a plurality of processing cores, the method comprising:

• providing a computer infrastructure being operable to test and configure a multi-core processor system chip comprising a plurality of processing cores by:
• setting at least one adjustable power supply component to provide a supply voltage having an initial nominal supply voltage value to each of the plurality of processing cores, the initial nominal supply voltage value specified to operate a processing core at a minimum reference clock speed pursuant to a design rule;
• for N iterations selecting a core of the plurality of processing cores and iteratively lowering a core set supply voltage provided by the at least one adjustable power supply component to the selected core and observing a clock speed of the selected core at the lowered supply voltage until an Nth observed clock speed generated responsive to an Nth lowered supply voltage is less than the minimum reference clock speed and setting the at least one adjustable power supply component to provide an (N-1)th lowered supply voltage as an operative supply voltage to the selected core;
• repeating the N iteration core selecting, the iterative supply voltage lowering and clock speed observing and the (N-1)th lowered supply voltage operative supply voltage setting for each unselected core of the processing core plurality until each of the cores has been selected, wherein different cores may have different core operative supply voltages set relative to the minimum reference clock speed;
• determining an overall power consumption value for the multi-core processor system with each of the plurality of cores operating at its respective set operative supply voltage;
• and
• passing the multi-core processor system chip if the overall power consumption value does not exceed a specified maximum power consumption value;
• or
• failing the chip.

A multi-core processor chip, comprising:

• a plurality of processing cores;
• a plurality of adjustable power supplies, each of the adjustable power supplies connected to a one of the plurality of processing cores and configured to provide a supply voltage to the one of the plurality of processing cores;
• a programmable controller in communication with the plurality of adjustable power supplies;
• and
• an inter-core voltage-level translation communication block component configured to enable the plurality of processing cores to function with divergent on-signal supply voltages supplied by the adjustable power supplies;
• wherein the programmable controller is configured to manufacturing yield test and configure the multi-core processor chip by:
• setting the adjustable power supplies to an initial nominal supply voltage value, the initial nominal supply voltage value specified as operating a processing core at a minimum reference clock speed pursuant to a design rule;
• select each of the plurality of processing cores and iteratively lowering a core set supply voltage provided by the selected core's adjustable power supply until an Nth observed clock speed generated by the core responsive to an Nth lowered supply voltage is less than the minimum reference clock speed and set the selected core adjustable power supply to provide an (N-1)th lowered supply voltage as an operative supply voltage to the selected core, wherein different cores may be configured to have different core operative supply voltages set relative to the minimum reference clock speed;
• and
• pass the multi-core processor system chip if an overall power consumption value for the multi-core processor system with each of the plurality of cores operating at its respective set operative supply voltage does not exceed a specified maximum power consumption value;
• or
• fail the chip.