US 2008/0176400 A1Published application

III-V Compound Semiconductor Substrate Manufacturing Method

AssigneeSumitomo Electric Industries, Ltd.

InventorsAkihiro Hachigo, Naoki Matsumoto, Takayuki Nishiura

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Abstract

Affords a III-V compound semiconductor substrate manufacturing method that enables enhancement of the substrate PL intensity. In such a III-V compound semiconductor substrate manufacturing method, first, the surface 3a of a wafer 3 is polished (polishing step). Second, the surface 3a of the wafer 3 is cleaned (first cleaning step S7). Next, the surface 3a of the wafer 3 is subjected to first dry-etching, employing a halogen-containing gas, while first bias voltage is applied to a chuck 24 for carrying the wafer 3. Subsequently, the surface 3a of the wafer 3 is subjected to second dry-etching, employing the halogen-containing gas (second dry-etching step S11), while second bias power lower than the first bias power is applied to the chuck 24.

Claims6

Dependent claims

A III-V compound semiconductor substrate manufacturing method, comprising:

a polishing step of polishing the surface of a platelike III-V compound semiconductor crystal;
a cleaning step, subsequent to said polishing step, of cleaning the III-V compound semiconductor crystal surface;
a first dry-etching step, subsequent to said cleaning step, of applying first bias power to an electrode for carrying the III-V compound semiconductor crystal, and meanwhile subjecting the crystal surface to first dry-etching employing a first halogen-containing gas;
and
a second dry-etching step, subsequent to said first dry-etching step, of applying second bias power smaller than the first bias power to the electrode, and meanwhile subjecting the III-V compound semiconductor crystal surface to second dry-etching employing a second halogen-containing gas.

2 more elements

Dependencies are inferred from the claim text.