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US 2008/0176343 A1Published application
Method For Smart Dummy Insertion To Reduce Run Time And Dummy Count
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsGwan Sin Chang, Yi-Kan Cheng, Cliff Hou
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Abstract
A method involves providing a circuit pattern, generating a density report for the circuit pattern that identifies a feasible area for dummy insertion, simulating a planarization process with the density report and identifying a hot spot on the circuit pattern, inserting a virtual dummy pattern in the feasible area and adjusting the density report accordingly, and thereafter simulating the planarization process with the adjusted density until the hot spot is eliminated.
Claims24
A method comprising:
- providing a circuit pattern;
- generating a density report for the circuit pattern that identifies a feasible area for dummy insertion;
- simulating a planarization process with the density report and identifying a hot spot on the circuit pattern;
- inserting a virtual dummy pattern in the feasible area and adjusting the density report accordingly;
- and
- simulating, after the inserting, the planarization process with the adjusted density until the hot spot is eliminated.
3 more elements
A method comprising:
- providing a circuit layout;
- generating a density report for the circuit layout to identify an area for dummy insertion;
- simulating a first planarization process that implements a first density insertion for inserting dummy patterns within the area and a second planarization process that implements a second density insertion for inserting dummy patterns within the area;
- and
- determining an optimal dummy insertion for the circuit layout by comparing a first thickness report from the first planarization process with a second thickness report from the second planarization process to identify a hot spot and a cold spot.
2 more elements
A semiconductor device comprising:
- a circuit layout having a plurality of regions, wherein each region has a local density associated with it;
- an area within the circuit layout that is available for dummy insertion;
- and
- an optimal dummy insertion formed within the area, wherein the optimal dummy insertion is configured by comparing a first simulated planarization process implementing a first density insertion with a second simulated planarization process implementing a second density insertion to identify a hot spot and a cold spot.
1 more element
Dependencies are inferred from the claim text.