Symmetrical Clock Distribution in Multi-Stage High Speed Data Conversion Circuits

A high speed bit stream data conversion circuit comprising:

• a first plurality of input ports that receive a first plurality of bit streams at a first bit rate;
• a plurality of data conversion circuits that receive the first plurality of bit streams and that produce at least one second bit stream at a second bit rate, wherein the number and bit rate of the first plurality of bit streams and the at least one second bit stream differ;
• a plurality of symmetrical data circuit pathways that include pairs of circuit pathways, and that transport the first plurality of bit streams from the first plurality of input ports, and to the plurality of data conversion circuits, wherein transmission times for the first plurality of bit streams on the plurality of symmetrical data circuit pathways are substantially equal;
• a clock distribution circuit that receives a data clock signal at a clock port located at a midpoint of the first plurality of input ports, and symmetrically distributes the data clock signal to the plurality of data conversion circuits along a plurality of symmetrical clock circuit pathways, wherein the symmetrical clock circuit pathways further include a central trunk coupled to the clock port and wherein the trunk is located between a first pair of circuit pathways, and symmetrical pairs of branches that extend from the trunk and couple to the data conversion circuits, and wherein clock transmission times associated with each symmetrical clock circuit pathway are substantially equal, and wherein the distributed data clock signal latches data in the data conversion circuits from the first plurality of bit streams to the second plurality of bit streams, and wherein the pairs of circuit pathways include a first pathway located on a first side of the trunk and a second pathway located on a second side of the trunk, wherein the second side is opposite the first side.