Time multiplexed bidirectional bus

A method for time-multiplexing first and second bidirectional data communication components for a data bus, the method comprising:

• providing a datalink;
• providing a clock signal for utilization by a datalink interface component, wherein the datalink interface component operatively connects to the datalink, wherein the datalink interface component operates in at least one of a first data communication state, a second data communication state, and a wholly inactive state;
• partitioning the clock signal into at least three clock cycles;
• transmitting data via the datalink from the first data communication component during the first data communication state, wherein the first data communication state exists during one of the at least three clock cycles;
• transmitting data via the datalink from the second data communication component during the second data communication state, wherein the second data communication state exists during one of the at least three clock cycles;
• and
• tri-stating the first and second data communication components during the wholly inactive state, wherein the wholly inactive state exists during one of the at least three clock cycles between that of the first and second data communication states.

A system for providing bidirectional communication for a data bus comprising:

• a datalink interface component configured to generate a clock signal, said datalink interface component being interfaced with a datalink and operating in at least one of a first data communication state, a second data communication state, and a wholly inactive state, said first data communication state existing during a first cycle of the clock signal and said second data communication state existing during a second clock cycle of the clock signal;
• wherein a first data communication component is configured to communicate via the datalink interface and a second data communication component is tri-stated during the first data communication state;
• wherein the second data communication component is configured to communicate via the datalink interface and the first data communication component is tri-stated during the second data communication state;
• and
• wherein the wholly inactive state exists on a third clock cycle of the clock signal, said third clock cycle existing between the first and second clock cycles, wherein the wholly inactive state causes the first and second data communication components to be tri-stated.