Multi-Stage Scheduler with Processor Resource and Bandwidth Resource Allocation

An apparatus, the apparatus comprising:

• a processing device comprising scheduling circuitry;
• the scheduling circuitry implementing a processor resource scheduling element and a bandwidth resource scheduling element;
• wherein the processor resource scheduling element schedules data blocks of multiple traffic flows for access to a processor resource using a first scheduling algorithm, the data blocks of the traffic flows being processed by the processor resource as scheduled by the first scheduling algorithm;
• and
• wherein the bandwidth resource scheduling element schedules processed data blocks of the traffic flows for access to a bandwidth resource using a second scheduling algorithm, the processed data blocks being provided to the bandwidth resource as scheduled by the second scheduling algorithm.

A communication system comprising:

• a network;
• a switch fabric;
• and
• a processing device coupled between the network and the switch fabric;
• wherein the processing device is operative to schedule data blocks of multiple traffic flows for access to a processor resource using a first scheduling algorithm, the data blocks of the traffic flows being processed by the processor resource as scheduled by the first scheduling algorithm;
• and
• wherein the processing device is further operative to schedule processed data blocks of the traffic flows for access to a bandwidth resource using a second scheduling algorithm, the processed data blocks being provided to the bandwidth resource as scheduled by the second scheduling algorithm.