Memory device and method having programmable address configurations
AssigneeMicron Technology, Inc.
InventorJ. Thomas Pawlowski
Life of this patent
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Abstract
A memory device includes a configurable address register having a first set of input buffers coupled to a first set on address bus terminals and a second set of input buffers coupled to a second set of address bus terminals. In a first addressing configuration, address signals are simultaneously applied to the address bus terminals in the first and second sets, and they are simultaneously stored in respective address registers. In a second addressing configuration, a plurality of sets of address signals are sequentially applied to the address bus terminals in only the first set of address bus terminals. Each set of address signals is then stored in a different address register.
Claims2
A configurable address buffer, comprising:
- a plurality of input buffers coupled to receive respective address signals, each of the input buffers passing the address signal received by the input buffer to an output terminal;
- a first address register coupled to the output terminals of a first subset of the input buffers to receive a corresponding subset of the address signals, the first address register storing the received address register signals responsive to a first enable signal;
- a signal routing device coupled to the output terminals of the input buffers in the first subset, the signal routing device further being coupled to the output terminals of a second subset of the input buffers to receive a corresponding subset of the address signals, the signal routing device being responsive to a first mode signal to couple address signals from the output terminals of the input buffers in the second subset to a set of output terminals, and being responsive to a second mode signal to couple address signals from the output terminals of the input buffers in the first subset to the set of output terminals, and;
- a second address register coupled to receive the address signals from the output terminals of the signal routing device, the second address register storing the received address register signals responsive to a second enable signal;
- and
- a control circuit operable to generate the first and second enable signals and the first and second mode signals, the control circuit being operable in a first mode to generate the first mode signal and to simultaneously generate the first and second enable signals, and being operable in a second mode to generate the second mode signal and to sequentially generate the first and second enable signals.
2-53. (canceled)
Dependencies are inferred from the claim text.