Multi-Port Dynamic Memory Structures
AssigneeInternational Business Machines Corporation
InventorsWing K. Luk, Brian L. Ji
Life of this patent
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Abstract
A dynamic random access memory circuit has at least one write bit line, at least one read bit line, a capacitive storage device, a write access device operatively coupled to the capacitive storage device and the at least one write bit line, a sense amplifier operatively coupled to the at least one read bit line and configured to generate an output signal, and a refresh bypass device operatively associated with the sense amplifier and the at least one write bit line so as to selectively pass the output signal to the at least one write bit line.
Claims21
A dynamic random access memory circuit comprising:
- at least one write bit line;
- at least one read bit line;
- a capacitive storage device;
- a write access device, said write access device being operatively coupled to said capacitive storage device and said at least one write bit line;
- a sense amplifier, said sense amplifier being operatively coupled to said at least one read bit line and configured to generate an output signal;
- and
- a refresh bypass device, said refresh bypass device being operatively associated with said sense amplifier and said at least one write bit line so as to selectively pass said output signal to said at least one write bit line
A dynamic random access memory circuit comprising:
- at least one write bit line;
- at least one read bit line;
- a capacitive storage device;
- a write access device, said write access device being operatively coupled to said capacitive storage device and said at least one write bit line;
- a first sense amplifier, said first sense amplifier being operatively coupled to said at least one read bit line and configured to generate an output signal;
- a refresh sense amplifier, said refresh sense amplifier being operatively coupled to said at least one write bit line and configured to generate a refresh sense amplifier output signal;
- and
- a refresh bypass device, said refresh bypass device being operatively associated with said refresh sense amplifier and said at least one write bit line so as to selectively pass said refresh sense amplifier output signal to said at least one write bit line.
A dynamic random access memory circuit comprising:
- at least one write bit line;
- at least one read bit line;
- a capacitive storage device;
- a write access device, said write access device being operatively coupled to said capacitive storage device and said at least one write bit line;
- and
- a refresh select bypass device, said refresh select bypass device being operatively coupled to said capacitive storage device and configured to selectively pass an indication of data stored in said capacitive storage device to said at least one write bit line while maintaining said data stored in said capacitive storage device.
A method for refreshing data in a dynamic random access memory circuit, comprising the steps of:
- reading said data, from a capacitive storage device of a memory cell of said circuit, into a sense amplifier, wherein said data is read from said capacitive storage device via a read port of said cell;
- passing said read data to a write port of said cell;
- and
- writing data from said write port to said capacitive storage device.
A method for performing a read operation when writing data to a dynamic random access memory circuit, comprising the steps of:
- writing said data to a capacitive storage device of a memory cell of said circuit from a data input signal;
- and
- passing data from said data input signal to a data output signal when a read address and write address identify said cell.
A method for refreshing data to a dynamic random access memory circuit, comprising the steps of:
- reading said data from a capacitive storage device of a memory cell of said circuit into a refresh sense amplifier, wherein said data is read from said capacitive storage device via an exclusive write port of said cell;
- and
- writing said data from said sense amplifier to said capacitive storage device.
Dependencies are inferred from the claim text.