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AssigneeInternational Business Machines Corporation
InventorsJohn Edward Barth, Paul C. Parries, William Robert Reohr, Matthew R. Wordeman
Estimating the term…
A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit. At least two block circuits are connected to a given pair of bank bit lines, the block circuits being configured such that a load on each bank bit line in the given pair of bank bit lines is substantially matched to one another.
A sense amplifier circuit for use in a memory circuit including multiple pairs of differential bit lines, the sense amplifier circuit comprising:
An integrated circuit including at least one sense amplifier circuit for use in a memory circuit including multiple pairs of differential bit lines, the at least one sense amplifier circuit comprising:
Dependencies are inferred from the claim text.